Unformatted text preview: CSE/EE 5/7385 Microcontroller Architecture and Interfacing HOMEWORK 6 1. Slide number 26 in the class notes entitled “Memory System Architecture” in week 12 shows a simple memory interface. You are to design a different memory interface that has the same architecture as slide 26, but uses different memory chips. You will use the following memory devices: -‐ Eight (8) SRAM chips that are 8M×4 bits capacity and have !oe and !we control signals identical to the SRAM chips on slide 26. (Note: !oe means that the ‘output enable’ signal is active low and !we means that the ‘write enable’ signal is active low.) -‐ Four (4) ROM chips that are 1M×8 bits capacity and have a !oe active-‐low output enable input. a) The SRAM chips each have a bidirectional data bus of m pins and a unidirectional address bus of n pins. What is the value of m and n? m = _____4____ n = ____23_____ b) The ROM chips each have a bidirectional data bus of m pins and a unidirectional address bus of n pins. What is the value of m and n? m = _____8____ n = _____20____ c) In terms of the memory map, the ROM memory is to occupy the address space with the lowest address of 0x00000000. What is the highest address in the memory map that the ROM memory occupies in the memory map? Give your answer in the form of eight (8) hexadecimal digits. (Note: assume a byte-‐addressable memory is being designed.) Highest ROM address = ___0x000FFFFF___ The highest address occurs when all 20 LS address bits are set, so this is 0x000FFFFF d) In terms of the memory map, the SRAM memory is to occupy the address space with the lowest address of 0xA0000000. What is the highest address in the memory map that the SRAM memory occupies in the memory map? Give your answer in the form of eight (8) hexadecimal digits. (Note: assume a byte-‐addressable memory is being designed.) Highest SRAM address = __0xA07FFFFF__ The highest address for the SRAM memory bank occurs when all 23 address bits are set: 0x007FFFFF. However, the SRAM memory space begins at 0xA0000000 so this must be added to the highest SRAM memory bank address to determine the highest memory map address: 0xA0000000+0x007FFFFF=0xA07FFFFF e) If this memory system is to support an ARM processor with a 32-‐bit address bus and a 32-‐bit bidirectional data bus, use the appropriate ARM processor signals and design a circuit that will be connected to the !oe inputs of the ROM memory chips. Your answer should be in the form of a digital logic combinational circuit. (Note: this is a portion of the circuitry that is inside the box labeled ‘control’ on slide 26 of the notes and produces the !ROMoe signal.) !oe should be asserted (active low) only when the 16 MSbs of the address bus are low since valid address ranges are 0x00000000 through 0x000FFFFF. That is, the least significant 16 bits of the address bus are don’t cares. The address decoder part selects valid address range for accessing the ROM bank and is produced by gate G1 that outputs the VALROM (active-‐high) signal. The ROM output enable signals must be synchronized with MCLK and must be accessed only when !r/w is low (since a ROM is a read-‐only device). Gate G2 uses !r/w, VALROM, and MCLK to produce the active low !ROMoe signal. f) On slide 26, the control circuit generates four (4) write enable signals for the four SRAM chips used in the example (!RAMwe0, !RAMwe1, !RAMwe2, !RAMwe3). How many !RAMwe signals will the control unit need to generate for the memory system you are designing? # of RAMwe signals = _____4______ We will still need only 4 signals because each SRAM chip contains half of a byte (1 nybble), so each pair of SRAM chips will support a single address to comprise one byte. The SRAM chips are used pairwise in a similar manner to the SRAM chips in slide 26. The !oe and !we inputs of each pair of SRAM chips are tied together effectively forming an 8-‐bit SRAM. For this reason only 4 signals are needed in the same way as slide 26. g) For each !RAMwe signal you identified above, give the corresponding circuit that uses appropriate inputs from the ARM processor. Each !RAMwe signal will be an output of a logic gate diagram and is inside the box labeled ‘control’ on slide 26. The !RAMwe signals depend on the MS 9 bits of the address bus since valid SRAM addresses are all between 0xA0000000 and 0xA07FFFFF. That is, the least significant (LS) 23 address bus bits are don’t cares. The gate labeled G1 serves as an address decoder that produces an intermediate signal VALRAM indicating a valid SRAM address is present. In addition to VALRAM, the !r/w ARM control output signal must be asserted high since RAMwe signals are only asserted when a write operation is occurring. Finally, the MAS[1:0] ARM control outputs signals are used to select which of the various SRAM chips are selected based on whether a byte, halfword, or word is being written. Since MAS[1:0] indicates a halfword write, but does not indicate whether the halfword is a MS halfword or a LS halfword, we must also use the lower address bit A. When A=12, a MS halfword is being written and when A=02, a LS halfword is being written. This is exactly the same portion of the circuit as shown in slide 32. The outputs of the OR gates are labeled PSEL (for pair select). The PSEL signals must be synchronized with the MCLK, the VALRAM, and the !r/w signals. h) Combine all of the logic circuits above into a single diagram that represents the entire circuit in the box labeled ‘control’ on slide 26. (Note: slide 32 is the similar type of circuit asked for here but that corresponds to slide 26). The only additional circuit needed in addition to those shown above is the circuit that produces the !RAMoe signal. This signal is asserted whenever an SRAM address is present (VALRAM is high) and when !r/w is asserted low indicating a read operation. !RAMoe must also be synchronized with the MCLK system clock signal. One additional gate is used and is shown as G3 below. 2. The AMBA bus supports pipelined accesses meaning that a new access can be initiated before the previous one is finished. Describe how this is possible for the AMBA bus. Accesses are comprised of two bus clock cycles. During the first cycle, the address is asserted and during the second, the data corresponding to the address is read or written. These cycles are referred to as the ‘address phase’ and the ‘data phase’ respectively. Pipelining is achieved by overlapping the address phase for a new access to occur during the same bus clock cycle as the data phase for the current access. An example is shown on slide 21 of the ‘Memory System Architecture’ notes. 3. Is it possible for a system using the AMBA bus to access a memory bank or an I/O device that has a response time slower than the HCLK clock cycle? If not, explain why using the appropriate AMBA bus signals in your response. If yes, explain why using the appropriate AMBA bus signals in your response. Yes, it is possible because the AMBA bus specification contains a signal HREADY that allows for wait states to be inserted during a bus transaction. An example is shown on slide 21 of the ‘Memory System Architecture’ notes. The memory system or I/O device can assert HREADY (active-‐low) to cause extra bus cycles to elapse between the address and data phases of a transaction. 4. The AMBA standard contains specifications for the AHB and the APB bus. The APB bus is intended for use with lower bandwidth peripherals. Why would an embedded system designer choose to use APB instead of AHB, that is what is the advantage offered by using APB? (Note: an incorrect answer is ‘because the peripheral is low bandwidth,’ you need to tell me why APB is advantageous compared to AHB for low bandwidth peripherals). AHB supports several high bandwidth data transfer modes and multi-‐mastering, whereas APB just supports basic transactions and a single bus-‐master. This means that the AHB bus controller interface is more complex than the corresponding APB interface. Since each device requires a bus controller interface, it is a waste of resources for low-‐bandwidth devices to contain this more complex AHB interface. 5. Why does the I2C bus require pull-‐up resistors on the SDA and SCL lines? Pull-‐up resistors are required because all devices connect to these lines with open-‐
collector output circuits. This means that I2C connected devices are only capable of pull the SDA and SCL lines to ground and high-‐impedance states when the bus is idle. The pull-‐up resistors allow the bus to be pulled to a high voltage state when the bus is idle. 6. Why does the I2C bus require all devices to connect to it with open-‐collector drivers? Open collector driving connections are required to enable the bus arbitration method. I2C bus arbitration depends on a wired-‐AND operation and the wired-‐AND occurs due to the open-‐collector connections. 7. When the I2C bus is operating in standard mode and the attached devices all have high rail voltages of VDD=3.3V, answer the following, give the following values. (Note: you will have to refer to the I2C specification that is linked to the class syllabus) Minimum Low-‐level Input Voltage = __________-‐0.5V_____________ Maximum Low-‐level Input Voltage = ___(0.3)(3.3)=0.99V______ Minimum High-‐level Input Voltage = ______(0.7)(3.3)=2.31V___ Maximum High-‐level Input Voltage = ______3.3+0.5=3.8V_______ The above values are obtained from Table 4 on page 31 of the Philips I2C Specification, v2.1. 8. The following voltages are present on the D+ and D-‐ lines of a USB 2.0 bus operating in full bandwidth mode. Give the bitstream that is being transmitted on the bus. time t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 D+ 3.6 3.6 0.3 3.6 3.6 3.6 0.3 3.6 0.3 0.3 D-‐ 0.3 0.3 3.6 0.3 0.3 0.3 3.6 0.3 3.6 3.6 State: J J K J J J K J K K Bits: 1 0 0 1 1 0 0 0 1 ...
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- Fall '08