13 SPI.pdf - 12-Feb-182:54 PM SPI EEL 3744 Menu SPI...

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12-Feb-18—2:54 PM 1 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz SPI EEL 3744 1 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz Menu • SPI Concepts >Problems in serial communications – Timing Synchronization: How do you line up the bit boundaries? – Message Synchronization: How do you line up messages? >Synchronous data solves first problem by sending clock along with message – SPI performs a “physical-level” form of serial communication >Section 11.4 in the S&HE Book Covers the SPI system Look into my ... See docs/examples on web-site: doc8331 (Sec 22), doc2595 68HC12 : SPI_Master.asm, SPI_Slave.asm, SPI_Master_Tab.asm, SPI_Out.asm EEL 3744 2 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz What is SPI? •SPI = Serial Peripheral Interface >Established by Motorola •Synchronous serial data link operating in full duplex mode >Signals are carried in both directions on separate wires •Communicate with many devices, including non- SPI devices •May be treated as a Master or a Slave Device
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12-Feb-18—2:54 PM 2 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz SPI EEL 3744 3 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz Simple SPI Setup •4 Interface Signals > SCK - Serial Clock Output for master Input for slave > SS (L) - Slave Select Input for slave Unrelated output for master > MOSI - Master Out/Slave In > MISO - Master In/Slave Out •May use 3 or 4 pins XXXX XXXX YYYY YYYY YYYY YYYY XXXX XXXX Initial After 8 SCK’s Initial After 8 SCK’s Master SPI Data Register Slave SPI Data Register Device1 Device2 Master Slave MOSI MOSI SCK SCK MISO MISO GND SS SS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 EEL 3744 4 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz 68HC12 : SPI Block Diagram Tech: Fig 14-11 M68HC12B/D Rev 8 Fig. 14-11
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12-Feb-18—2:54 PM 3 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz SPI EEL 3744 5 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz XMEGA SPI • System consists of two shift registers and a master clock generator • Data is shifted out the master’s MISO pin • Data is shifted in the master’s MOSI pin See doc8331, Fig 22-1 EEL 3744 6 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz SPI Data Transfer • SPI Master initiates and controls all data transfer • Communication cycle is initiated by pulling the slave select low for the desired slave > It is possible to ignore the SS pin and have the slave on at all times • All data transfer is coordinated by SCK • Data transfer is simply initiated by a Master writing data to the SPI data register • To get input data only to a Master (i.e., no data to send to a Slave), just send “junk” data to the SPI data register
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12-Feb-18—2:54 PM 4 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz SPI EEL 3744 7 University of Florida, EEL 3744 – File 13 © Dr. Eric M. Schwartz SPI Details Message Length: 8-bits For many SPI systems, the shift Register can be either (in XMEGA, determined by DORD in the SPI CTRL register) > MSB to LSB > LSB to MSB
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