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UANDISTAR Code No: V0423/R07 II B.Tech II Semester, Regular Examinations, Apr - 2011 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. a) Convert (AB6.13) 16 into its octal equivalent and Convert (675.42) 8 into base-16 number. (8M) b) Convert the gray code number 10101111 into binary number and convert the decimal number 78.216 into BCD format. (8M) 2. a) Convert the given expressions into canonical SOP form i) f= AB + BC + CA (ii) f = A+ AB + ABC (8M) b) Simplify the following expressions using k-map i) f(A,B,C,D) = g153 m(0,1,3,7,15) + g153 d(2,11,12) ii) f(A,B,C,D) = g652 M(0,2,6,8,12) + g652 d(3,4,7,10,14) (8M) 3. Find the minimal expression using tabulation method for the given function F(A,B,C,D,E) = g153 m (1,2,12,13,15,17,18,19,20,21,23,24,25,27,29,31) (16M) 4. a) Design and draw the circuit diagram of BCD to binary code converter. (8M) b) Design and draw the circuit diagram of an octal to binary priority encoder. (8M) 5. a) Design and draw the circuit diagram of a BCD to Excess-3 code converter using PLA. (8M) b) Give the comparison between PROM, PAL and PLA with respect to various performance features. (8M) 6. a) Give and explain the realization of JK- flip flop using SR- flip flop. (8M) b) Design and draw the logic diagram for MOD-6 ripple counter. Give the design considerations. (8M) 1 of 2 SET - 1
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UANDISTAR Code No: V0423/R07 7. Determine the minimal state equivalent of the state table given below and find the minimum length sequence that distinguishes states A and F. (16M) Present state Next State, Z X = 0 X= 1 A B C D E F G E,0 C,0 B,0 G,0 F,1 E,0 D,0 C,0 A,0 B,0 A,0 B,0 D,0 G,0 8. The digital system to be designed consists of two registers R 1 , R 2 and a flip flop, E. The system counts number of 1’s in the number loaded into register R 1 and sets register R 2 that number. Draw the ASM chart and design the control logic using multiplexers. (16M) 2 of 2 SET - 1
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UANDISTAR Code No: V0423/R07 II B.Tech II Semester, Regular Examinations, Apr - 2011 SWITCHING THEORY AND LOGIC DESIGN
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