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Code No: V0423    II B.Tech II Semester (R07) Regular/supply Examinations, Apr- 2010    SWITCHING THEORY AND LOGIC DESIGN  (Electronics and Communications Engineering)    Time: 3 Hours                                             Max Marks: 80  Answer any FIVE Questions  All Questions carry equal marks      1.   a) A 4n-bit number is represented by an n-digit hexadecimal number H. Prove that the one’s  complement of B is represented by 15’s complement of H                                (6M)  b) Discuss how to construct distance-6 code with 4-information bits? Write a list of its code  words.                     (10M)    2.   a) Simplify the following using switching Algebra theorems?       (8M)      B A B A B A B A F ii E C B A E C B A E D B A D C B A B A F i . . . . . . . . . . . . . . . . . . .   b) A digital system that includes three signals X, Y and Z has been designed so that at all  times at least two of these signals are 1. In this system how many different three variable  logic functions F(X, Y, Z) are there? Functions are considered to be different only if their  outputs differ for at least one of the normally occurring input combinations. Write a  simplified algebraic expression for each combination        (8M)       3.   Using Karnaugh maps, find minimal SOP expressions for the following logic functions.    a)   F =    w,x,y,z  ( 0,1,2,3,7,8,10,11,15)            (4M)  b)   F =   w,x,y,z  ( 4,5,9,13,15) + d(0,1,7,11,12)                                    (6M)  c)   F      A,B,C,D  (1, 5, 12, 13, 14, 15) + d(7, 9)          (6M)    4.   a) What is decoder? How do you convert a decoder in to a De-Multiplexer   (8M)  b) F(w,x,y,z) =   m (1,4,5,6,7,9,14,15) Realize using De-Multiplexer     (8M)                                         5.   a) Draw the logic diagram of Programmable Logic Array? Explain its operation   (10M)               b) Realize threshold function   z y x f 5 . 1 3 5 . 2          (6M)    6.   a) Draw the circuit of JK Flip Flop using NAND gates and explain its operation.  (8M)    b) Draw and explain the working of 4 bit UP/DOWN synchronous counter   (8M)    7.   Design a clocked synchronous state machine using D flip flops of the following state/output  table? Use two state variables, Q1 Q2 with state assignments A=00, B=01, C=11, D=10.                         (16M)  1 of 2    ^dͲϭ Please purchase PDF Split-Merge on .
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Code No: V0423                           
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