SNUG Boston 2004
1
Modeling FIFO Channels Using SystemVerilog Interfaces
Modeling FIFO Communication Channels Using
SystemVerilog Interfaces
Stuart Sutherland
Sutherland HDL, Inc.
[email protected]
ABSTRACT
The Verilog Hardware Description Language (Verilog HDL) does not have a direct equivalent to
SystemC channels.
These channels are often used for modeling abstract, high-level
communications between modules. This paper shows how the SystemVerilog extensions to
Verilog can be used to model high-level communication channels.
SystemVerilog extends the Verilog HDL with a powerful
interface
construct. This construct
provides a way to encapsulate the communication between the major blocks of a design.
Interfaces can be used for more than just data encapsulation, however. An interface can also
contain procedural code, tasks and functions. This paper provides a brief tutorial on
SystemVerilog interfaces, and then delves into one way in which interfaces can be used for high-
level modeling. A FIFO channel is used as the basis for examples in this paper, but the concepts
presented can be applied to other types of communication channels, such as a mutex channel. The
FIFO behavior is modeled using other powerful SystemVerilog constructs: mailboxes and queues.
The interface FIFO channel is modeled to be reconfigurable; it can be configured to pass data of
any data type, including integers, reals, vectors of any size, and user-defined types. The paper also
discusses synthesizing SystemVerilog interfaces and the modeling constructs used in the
examples shown.
