HW7.pdf - CprE 381 Homework 7 [Note: The first couple of...

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CprE 381 Homework 7[Note: The first couple of questions are intended to help you familiarize yourself with pipelining.The third question will help you prepare for the exam by looking through lecture notes andonline quizzes and then thinking which questions I might ask. The final question should help youconnect the topics we’ve been learning about with real world implications and should be a funreality check for halfway through the semester.]1.Pipelining Cycle TimeAssuming the following worst-case latencies for components, what is the cycle time forthe pipelined processor in Figure 4.51 on page 304 of P&H? You must quantitativelyjustify your answer (e.g., specify what set’s the cycle time and why it set’s the cycletime).I-MemAdderMUXALURegReadD-MemSign-ExtendShift-Left-2ControlALUControlAND gate200ps70ps20ps90ps90ps250ps10ps5ps40ps20ps10ps2.Pipeline SimulationFor each of the modules from Figure 4.51 (page 304 of P&H) that are listed in the table

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Term
Spring
Professor
ZAMBRENO
Tags
Central processing unit, Instruction pipeline, Cycle Time, Adder MUX ALU, following worst case latencies, real world implications

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