Unit2b.pdf - 211 Computer Architecture Fall 2015 Instructor Prof David Menendez Topics Hardware-Software Interface Assembly Programming Reading Chapter

Unit2b.pdf - 211 Computer Architecture Fall 2015 Instructor...

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Instructor: Prof. David Menendez Topics: Hardware-Software Interface Assembly Programming Reading: Chapter 3 211: Computer Architecture Fall 2015
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Programming Meets Hardware High-Level Language Program Assembly Language Program Machine Language Program movl $1, -8(%ebp) movl $2, -12(%ebp) movl -8(%ebp), %eax movl %eax, -16(%ebp) movl -12(%ebp), %eax movl %eax, -8(%ebp) movl -16(%ebp), %eax movl %eax, -12(%ebp) movl -16(%ebp), %eax movl %eax, 12(%esp) movl -12(%ebp), %eax movl %eax, 8(%esp) movl -8(%ebp), %eax movl %eax, 4(%esp) 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 02 00 03 00 01 00 00 00 f0 82 04 08 34 00 00 00 c4 0c 00 00 00 00 00 00 34 00 #include <stdio.h> int main() { int x, y, temp; x=1; y=2; temp =x; x=y; y=temp; printf("%d %d %d\n",x,y,temp); } ISA Compiler Assembler How do you get performance?
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Rutgers University David Menendez 3 Performance with Programs (1) Program: Data structures + algorithms (2) Compiler translates code (3) Instruction set architecture (4) Hardware Implementation
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Rutgers University David Menendez 4 Instruction Set Architecture (1)Set of instructions that the CPU can execute(1)What instructions are available?(2)How the instructions are encoded? Eventually everything is binary.(2)State of the system (Registers + memory state + program counter)(1)What instruction is going to execute next(2)How many registers? Width of each register?(3)How do we specify memory addresses? Addressing modes (3) Effect of instruction on the state of the system
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Rutgers University David Menendez 5 IA32 (X86 ISA) There are many different assembly languages because they are processor-specific IA32 (x86) x86-64 for new 64-bit processors IA-64 radically different for Itanium processors Backward compatibility: instructions added with time PowerPC MIPS We will focus on IA32/x86-64 because you can generate and run on iLab machines (as well as your own PC/laptop) IA32 is also dominant in the market although smart phone, eBook readers, etc. are changing this
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Rutgers University David Menendez 6 X86 Evolution 8086 – 1978 – 29K transistors – 5-10MHz I386 – 1985 – 275K transistors – 16-33 MHz Pentium4 – 2005 – 230M transistors – 2800-3800 MHz Haswell – 2013 – > 2B transistors – 3200-3900 MHz Added features Large caches Multiple cores Support for data parallelism (SIMD) eg AVX extensions
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Rutgers University David Menendez 7 CISC vs RISC CISC: complex instructions : eg X86 Instructions such as strcpy/AES and others Reduces code size Hardware implementation complex? RISC: simple instructions: eg Alpha Instructions are simple add/ld/st Increases code size Hardware implementation simple?
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Rutgers University David Menendez 8 Aside About Implementation of x86 About 30 years ago, the instruction set actually reflected the processor hardware E.g., the set of registers in the instruction set is actually what was present in the processor As hardware advanced, industry faced with choice Change the instruction set: bad for backward compatibility Keep the instruction set: harder to exploit hardware advances Example: many more registers but only small set introduced circa 1980 Starting with the P6 (PentiumPro), IA32 actually got implemented by Intel using an “interpreter” that translates IA32 instructions into a simpler “micro” instruction set
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P6 Decoder/Interpreter
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  • Fall '15
  • SantoshNagarakatte
  • Computer Architecture, X86, Processor register, Call stack, Rutgers University, Addressing mode, Prof. David Menendez

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