ELEC2142_Week 8_9.pdf

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ELEC2142: Embedded Systems Design W EEK 8/9-2016 Exceptions and interrupts
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2 Overview Definitions Hardware interrupts and error conditions Exception modes Vector table Exception handlers SWI Interrupts – IRQ and FIQ Vector interrupt controller A complete structure for handlers
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3 Definitions Exception is an event that requires the CPU to perform an action breaking the normal flow of a program. Benign events like someone moving a mouse or pushing a button Catastrophic faults such as bus error Exceptions should be anticipated to help find the cause of the problem during application development or to plan for graceful shutdown. Exceptions can be categorized into two large classes: interrupts and error conditions Interrupts are exceptions raised asynchronously by I/O devices so that they can be served by the CPU. Software Interrupt is an exception that can be raised within the application using SWI instruction. It is a user defined synchronous exception.
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4 Hardware Interrupts (I/O) An interrupt is an efficient way that I/O ( peripheral) devices use to get the attention of the microprocessor. There are two interrupt lines that are connected to the control unit of the CPU. They are a low priority interrupt (IRQ) and a high priority interrupt called FIQ I/O interrupts are asynchronous More information needs to be conveyed An I/O interrupt is not associated with any instruction, but it can happen in the middle of any given instruction
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5 Hardware Interrupts External lines for I/O Interrupt
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6 ERROR CONDITIONS Error exceptions occur quite often in an embedded system. So often that software needs to be sufficiently robust to handle them. Undefined instruction Floating-point instructions and emulate them in software. Data aborts occurs when the processor attempts to grab data in memory that does not physically exist occurs when the processor attempts to write data in read only memory region Prefetch abort occurs when the processor attempts to grab an instruction from a memory and something goes wrong
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7 Exception sources in ARM Reset : Occurs when the processor reset pin is asserted. (Signalling power-up) Undefined Instruction : Occurs if the processor, does not recognize the currently executing instruction. Software Interrupt (SWI): This is a user-defined intentional synchronous interrupt instruction. Prefetch Abort : Occurs when the processor attempts to execute an instruction that was not fetched, because the address was illegal. Data Abort : Occurs when a data transfer instruction attempts to load or store data at an illegal address. IRQ : Occurs when the processor external Interrupt ReQuest pin is asserted FIQ : Occurs when the processor external Fast Interrupt reQuest pin is asserted
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8 ARM modes of operation 10000 User Normal user code 10001 FIQ Processing fast interrupts 10010 IRQ Processing standard interrupts 10011 SVC
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