Lab 7 ECEN 248.pdf - Lab 7 Introduction to Behavioral...

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Lab 7: Introduction to Behavioral Verilog and Logic Synthesis Tjader De Alba ECEN 248-510 TA: Saurav Kumar Sahu Date: March 8, 2018
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Objectives: In this lab we will at an even higher level of abstraction in Verilog HDL than last week called behavioral modeling. In the first experiment we will recreate the multiplexers described in the last lab using Verilog. In the second experiment we will use behavioral Verilog to describe binary encoders and decoders. In this lab we will also be introduced to logic synthesis, the process of translating HDL code into implementable digital logic. Lastly, we will program a ZYBO board to test the components described in Verilog. Design: Verilog will be written for a 2:4 binary decoder, 4:2 binary encoder, and 4:2 priority encoder.
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Results: By the end of the lab I had successfully tested the 2:4 decoder, 4:2 encoder, and the priority encoder on the FPGA. The correct LEDs were lit up on the ZYBO board corresponding to which switches were thrown or which buttons were pressed.
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