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Lab 6 ECEN 248.pdf

Lab 6 ECEN 248.pdf - Lab 6 Introduction to Logic Simulation...

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Lab 6: Introduction to Logic Simulation and Verilog Tjader De Alba ECEN 248-510 TA: Saurav Kumar Sahu Date: March 1, 2018
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Objectives: The purpose of this lab was to be introduced to the concept of digital circuit simulation, and in the process learn about Verilog HDL. This is a step-up from breadboarding. To do this we created a 2:1 Mux, a 4-bit wide 2:1 Mux, a full adder, an adder/subtraction unit, and lastly a ALU. We then proved these programs by simulations and completing sever tests for each. Design: In the lab we transferred a 2:1 Mux, a 4-bit wide 2:1 Mux, a full adder, an adder/subtraction unit, and lastly a ALU to Verilog. The code and waveforms for each are shown below. Results: After writing out a program it was tested by running it through a simulation. Each program produced its own waveforms as seen below in the “Questions” portion of the lab report.
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Conclusion: Verilog and simulations proved to be an effective way to implement more complex circuits than breadboarding. Through Verilog a person can write and debug a program that for breadboarding would take hours, many wires, and be twice as hard to troubleshoot.
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