Lab 1 ECEN 248.pdf - Lab 1 Digital Logic Gates Tjader De...

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Lab 1: Digital Logic Gates Tjader De Alba ECEN 248-510 TA: Saurav Kumar Sahu Date: January 25, 2018
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Objectives: In this lab I learned about gate behavior and logic interpretation. I also learned about the basics of circuit wiring and troubleshooting. I accomplished this through exploring basic logic gates talked about in lecture. Design: In the lab we used the 7400 series of logic gates. In bread-boarding the digital circuits in lab I used the Dual-Inline Package (DIP). I tested multiple gates and observed the voltage output as either high or low. Results: The logic gates behaved as expected during the lab. A high voltage was read when expected, and a low voltage was read when expected. The tables below represent the results. Table 1: Truth Table for Inverter (NOT Gate) A (High/Low) Y (Volts) Y (High/Low) Low 3.9 High High .132 Low Table 2: Truth Table for AND & OR Gates A (H/L) B (H/L) AND2 (V) AND2 (H/L) OR2 (V) OR2 (H/L) L L .0988 L .0467 L L H .0982 L 4.02 H H L .0982 L 4.02 H H H 4.45 H 4.02 H Table 3: Truth Table for NAND, NOR, & XOR Gates
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