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Unformatted text preview: 2018/2/5 Take Test: Quiz 3 — 34359.1182 Blackboard @ SU Courses Organizatic [—1 ﬂ Assignments Take Test: Quiz 3 Take Test: Quiz 3 Test Information Description
Instructions Timed Test This test has a time limit of 2 hours.You will be notified when time expires, and you may continue or submit.
Warnings appear when half the time, 5 minutes, 1 minute, and 30 seconds remain. Multiple Attempts This test allows 2 attempts. This is attempt number 1.
Force Completion This test can be saved and resumed later. The timer will continue to run if you leave the test. Remaining Time: 1 hour, 59 minutes, 55 seconds. a Question Completion Status: Catherine Chin QUESTION 1 10 points Assume that individual stages of a datapathhave the following latencies: The clock cycle time of pipelined processor is ; The clock cycle time of non-pipelined processor is QUESTION 2 10 points As compared to a single-cycled datapath, a pipelined datapath has lower latency and higher throughput.
0 True 0 False QUESTION 3 10 points ADD instruction requires data memory access.
0 True 0 False QUESTION 4 10 points If there are 5 stages in a pipeline, then 5 is the maximum possible speedup.
0 True 0 False QUESTION 5 10 points
Which of the following is correct for a load instruction?
0 MemtoReg should be set to cause the correct register destination to be sent to the register ﬁle.
0 We do not care about the setting of MemtoReg for loads. 0 None of the others. httpszllblackboard.syracuse.edu/webapps/assessment/take/launch.jsp?course_assessment_id=_102601_1&course_id=_383804_1&content_id=_... Save Answer Save Answer Save Answer Save Answer Save Answer 1/2 2018/2/5 Take Test: Quiz 3 — 34359.1182 O MemtoReg should be set to cause the data from memory to be sent to the register ﬁle. QUESTION 6 Magnetic disks are volatile storage devices.
0 True 0 False QUESTION 7 RAW hazard is a control hazard.
0 True 0 False QUESTION 8 Data dependencies can always be avoided by a bypass logic.
0 True O False QUESTION 9 RAID 5 can recover from a two-disk failure. 0 True
O False QUESTION 10 nextPC=PC+_ Click Save and Submit to save and submit. Click Save All Answers to save all answers. httpszllblackboard.syracuse.edu/webapps/assessment/take/launch.jsp?course_assessment_id=_102601_1&course_id=_383804_1&content_id=_... 10 points 10 points 10 points 10 points 10 points Save All Answers Save and Submit Save Answer Save Answer Save Answer Save Answer Save Answer 2/2 ...
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- Spring '08
- Computer Architecture, Central processing unit, Instruction pipeline, clock cycle time