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Unformatted text preview: 2018/1/29 Take Test: Quiz 2 — 34359.1182 Blackboard @ SU Courses Organizatior g Chemir‘? 2“” ﬁ Assignments Take Test: Quiz 2 7 Take Test: Quiz 2 Test Information Description
Instructions Timed Test This test has a time limit Of 2 hours.YOu will be notiﬁed when time expires, and you may continue or submit.
Warnings appear when half the time, 5 minutes, 1 minute, and 30 seconds remain. Multiple Attempts This test allows 2 attempts. This is attempt number 1.
Force Completion This test can be saved and resumed later. The timer will continue to run if you leave the test. Remaining Time: 1 hour, 50 minutes, 19 seconds. as Question Completion Status: QUESTION 1 10 points Pipelining increases overall instruction throughput but also increases individual instruction latency.
g) True C) False QUESTION 2 10 points Name dependencies can be completely eliminated by a hardware mechanism at run-time.
@ True 3 False QUESTION 3 10 points Predicting branches at runtime by using run-time information, is known as 0 Static branch prediction
0 Stall prediction
@ Dynamic branch prediction 0 None of the above QUESTION 4 10 points Simplest scheme to handle branches is to O Flush pipeline
0 Freezing pipeline
0 Depth of pipeline
® Both a and b QUESTION 5 10 points Branch, MemWrite and MemRead are control lines set Of 0 Instruction decode Click Save and Submit to save and submit. Click Save All Answers to save all answers. Save All Answers Save and Submit ... 1/2 2018/1/29 Take Test: Quiz 2 — 34359.1182 v llIallubllUll run.” QUESTION 6 10 points Loops with no inter-iteration (loop-carried) dependencies can be executed in parallel.
3 False QUESTION 7 10 points Data fonivarding can resolve all data hazards.
3 True 5) False QUESTION 8 10 points Load and store instructions, sum of contents of base register and sign-extended Offset is used as O a register number
© a memory address
0 an operand O operator QUESTION 9 10 points A group Of students were debating the efﬁciency of the ﬁve-stage pipeline when one student pointed out that not all instructions
are active in every stage of the pipeline. After deciding to ignore the effects of hazards, they made the following four
statements. Which ones are correct? i Instead of trying to make instructions take fewer cycles, we should explore making the pipeline longer, so that instructions
take more cycles, but the cycles are shorter. This could improve performance. : You cannot make ALU instructions take fewer cycles because of the writeback of the result, but branches can take fewer
cycles, so there is some Opportunity for improvement. K Trying to allow some instructions to take fewer cycles does not help, since the throughput is determined by the clock cycle;
the number of pipe stages per instruction affects latency, not throughput. I I Allowing branches and ALU instructions to take fewer stages than the ﬁve required by the load instruction will increase
pipeline performance under all circumstances. QUESTION 10 10 points Ideal CPI (Cycle per instruction) on a pipelined processor is almost always
1 l Click Save and Submit to save and submit. Click Save All Answers to save all answers. Save All Answers Save and Submlt ... 2/2 ...
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- Summer '16
- Instruction pipeline, Dynamic branch