468Spring18_hw7_sol.pdf - ECEN 468 Advanced Digital System...

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ECEN 468 Advanced Digital System Design Spring 2018 Homework 7 Solution 1. (5 points) Find error module something_wrong( y_out, x1, x2 ); output y_out; input x1, x2; ‘define delay1 3; ‘define delay2 4; ‘define delay3 5; nand #( delay1, delay2, delay3 ) ( y_out, x1, x2 ); endmodule Solution: (1).Delete the symbol ‘;’ on define statements (2). Exchange the define to `define. (3). Turn-off delay is not allowed in non-three state gate. (Remove one of three define variables or exchange the symbol ‘,’ to ‘:’ for min-typ- max delay expression) ----------------------------------------- 2. (5 points) Determine the time values in simulation `timescale 10ns/10ps 2.437 `timescale 1ns/100ps 2.437 Solution: ` timescale
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  • Fall '08
  • JiangHu
  • It, Cybernetics, time value, min-typmax delay expression, non-three state gate, 10ps time value

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