第七章(3).ppt - Digital Logic Design and Application...

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1 Chapter 7 Sequential Logic Design Principles ( 时序逻辑设计原理 ) Latches and Flip-Flops ( 锁存器和触发器 ) Clocked Synchronous State-Machine Analysis ( 同步时序分析 ) Clocked Synchronous State-Machine Design ( 同步时序设计 ) Digital Logic Design and Application ( 数字逻辑设计及
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2 T Flip-Flop (T 触发器 ) 在每个时钟脉冲有效沿都会改变状态(翻转) Q Q T T toggle 触发器 EN Q T Q T flip-flop with enable T Q Digital Logic Design and Application ( 数字逻辑设计及
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3 T Flip-Flop Q Q T T flip-flop with enable Q* = EN·Q’ + EN’·Q EN Q T Q 说明: 传统中文教材中: 具有使能端的 T 触发器常叫 T 触发 T 触发器常叫 T’ 触发器 Digital Logic Design and Application ( 数字逻辑设计及 T 触发器的特征方程为 Q* = Q’
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4 T Q* = T·Q’ + T’·Q Q Q T 说明: 有的书上 T 触发器的特征方程写 为: 0 1 T 保持 翻转 Q* 功能表
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5 Use a D/J-k Flip-Flop to Design a T Flip-Flop ( 利用 D J-K 触发器实现 T 触发 )
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