第六章(1).ppt - Digital Logic Design and Application 1...

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1 第四章 组合逻辑设计原理 开关代数 公理、定理、逻辑函数的表示 组合电路分析 得到指定电路的功能(公式法化简) 组合电路综合 根据命题,得到电路实现(卡诺图化简) 定时冒险 Digital Logic Design and Application ( 数字逻辑设计及
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2 Chapter 6 Combinational Logic Design Practices ( 组合逻辑设计实践 ) Documentation Standard and Circuit Timing ( 文档标准和电路定时 ) Commonly Used MSI Combinational Logic Device ( 常用的中规模组合逻辑器件 ) Digital Logic Design and Application ( 数字逻辑设计及
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3 第 6 章教学大纲要求 重点学习掌握:学习利用基本的逻辑门完成规定的 组合逻辑电路的设计任务:如译码器、编码器、多路选 择器、多路分配器、异或门、比较器、全加器。学习利 用基本的逻辑门和已有的中规模集成电路( MSI )逻 辑器件如译码器、编码器、多路选择器、多路分配器、 异或门、比较器、全加器、三态器件等作为设计的基本 元素完成更为复杂的组合逻辑电路设计的方法。 Digital Logic Design and Application ( 数字逻辑设计及
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4 6.1 Documentation Standard ( 文档标准 ) Structure Thinking ( 结构化的理念 ) Specification: Description of Interface and Function ( 说明书:接口及功能描述 ) Block Diagram: System s Major Function Module and their Basic Interconnections ( 方框图 :主要功能模块及其互联 P345 6-1) Schematic Diagram [ 原理图 P360 6-17 ] Digital Logic Design and Application ( 数字逻辑设计及
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5 6.1 Documentation Standard ( 文档标准 ) Timing Diagram [ 定时图 P363 6-19 ] Structure Logic Device Description ( 结构化逻辑器件描述 ) Circuit Description : Explains how the circuit works internally. ( 电路描述: 解释电路内部如何工作 ) Digital Logic Design and Application ( 数字逻辑设计及
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6 Gate Symbols ( 门的符号 ) & ≥1 1 Digital Logic Design and Application ( 数字逻辑设计及
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7 Signal Name and Active Levels ( 信号名和有效电平 ) Name a Signal ( 信号的命名 ) An Active Level Associated with a Signal ( 与信号相关的有效电平 ) Active High (高电平有效 Active Low
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