# 第七章(2).ppt - Digital Logic Design and Application...

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1 Chapter 7 Sequential Logic Design Principles ( 时序逻辑设计原理 ) Latches and Flip-Flops ( 锁存器和触发器 ) Clocked Synchronous State-Machine Analysis ( 同步时序分析 ) Clocked Synchronous State-Machine Design ( 同步时序设计 ) Digital Logic Design and Application ( 数字逻辑设计及

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2 锁存器与触发器 Q QL R S Q QL S_L R_L S R C D C 具有使能端的 S-R 锁存器 S-R 锁存 D 锁存器 S-R 锁存 有约束条件 Review of Last Class ( 内容回 ) Digital Logic Design and Application ( 数字逻辑设计及
3 Flip-Flops ( 触发器 ) Change its outputs only at the Rising or Falling Edge of a controlling CLK signal. ( 只在时钟信号的边沿改变其输出状态 ) CLK Positive- Edge Rising-Edge ( 正边沿 上升沿 ) Negative- Edge Falling- Edge ( 负边沿 下降沿 ) Digital Logic Design and Application ( 数字逻辑设计及

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4 Flip-Flops ( 触发器 ) 从功能上分 D 触发器、 S-R 触发器、 J-K 触发器、 T 发器 从结构上分 主从结构触发器、边沿触发器 其他类型触发器 带使能端的触发器、扫描触发器 施密特触发器、单稳态触发器 Digital Logic Design and Application ( 数字逻辑设计及
5 D Flip-Flops (D 触发器 ) D Q C Q D Q C Q Q QL D CLK CLK=0 时， CLK=1 时， 主锁存器工作，接收输入信号

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• Spring '14
• JiangChaoshu

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