第七章(4).ppt - Digital Logic Design and Application...

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1 Chapter 7 Sequential Logic Design Principles ( 时序逻辑设计原理 ) Latches and Flip-Flops ( 锁存器和触发器 ) Clocked Synchronous State-Machine Analysis ( 同步时序分析 ) Clocked Synchronous State-Machine Design ( 同步时序设计 ) Digital Logic Design and Application ( 数字逻辑设计及
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2 Sequential Logic Circuit ( 时序逻辑电 ) Feedback Sequential Circuit 反馈时序 电路 采用“ 门电路+反馈回路 ”实现记忆功能 State Machine 状态机 用触发器构造电路,用时钟控制状态转换 CLK t per t H t L 周期: t per 频率: 1/ t per 占空比: t H /t per t L /t per —— Finite-State Machine FSM, 有限状态 概念:时钟周期、时钟频率、占空比、时钟触发沿 Digital Logic Design and Application ( 数字逻辑设计及
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Clock Signal ( 时钟 信号 ) 激励方程 或驱动方程 Excite equation 3 Sequential Logic Circuit Structure ( 时序逻辑电路结构 ) 下一 状态 逻辑 F 状态 存储器 时钟 Output Logic ( 输出 逻辑 ) G Inputs ( 输入 ) Output 输出 Exci- tation ( 激励 ) Current State ( 当前 状态 ) 下一状态: F (当前状态,输入) 输出: G (当前状态,输入) 组合 电路 状态存储器:由激励信号得到下一状态 输出方程 Output equation 转移方程 Transition equation —— 状态机结构 Digital Logic Design and Application ( 数字逻辑设计及
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4 同步 时序电路 异步 时序电路 —— 时钟同步状态机 存储元件状态的变化是在 同一时钟 信号操作下 同时 发生的 存储元件状态的变化 不是同时 发生的 Mealy Moore 输出信号取决于存储电路状态和输入信号 输出信号仅取决于存储电路状态 Sequential Logic Circuit ( 时序逻辑电 ) Digital Logic Design and Application ( 数字逻辑设计及
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5 下一 状态 逻辑 F 状态 存储器 时钟 输出 逻辑 G 输入 输出 时钟 信号 激励 当前状态 下一 状态 逻辑 F 状态 存储器 时钟 输出 逻辑 G 输入 输出 时钟 信号 激励 当前状态 输出 流水线 存储器 时钟 Moore 机:输出只与状态有关 Mealy 机:输出取决于状态和输入 输出
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6 7.3 Clocked Synchronous State Machine Analysis ( 时钟同步状态机分 ) 基本步骤: 确定 下一状态 函数 F 输出 函数 G F 代入触发器的 特征方程 得到下一状态 Q* 利用 Q* G 构造状态 / 输出表 画出 状态图 、波形图(可选) 描述电路 功能 Digital Logic Design and Application ( 数字逻辑设计及
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7 EN EN’ Q0 Q0’ Q1 Q1’ EN MAX Q0 Q1 CLK D0 D1 当前状态 激励 输出 输入 时钟信号 下一状态逻辑 产生激励信号 状态存储器 输出逻辑 Example: Clocked Synchronous State Machine Analysis (D Flip- Flop)
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8 EN
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  • Spring '14
  • JiangChaoshu

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