# 第七章(1).ppt - Digital Logic Design and Application...

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1 Chapter 7 Sequential Logic Design Principles ( 时序逻辑设计原理 ) Latches and Flip-Flops ( 锁存器和触发器 ) Clocked Synchronous State-Machine Analysis ( 同步时序分析 ) Clocked Synchronous State-Machine Design ( 同步时序设计 ) Digital Logic Design and Application ( 数字逻辑设计及

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2 Basic Concepts ( 基本概念 ) Logic Circuits are Classified into Two Types ( 逻辑电路分为两大类 ) Combinational Logic Circuit 组合逻辑电路 Sequential Logic Circuit 时序逻辑电路 Digital Logic Design and Application ( 数字逻辑设计及
3 Basic Concepts ( 基本概念 ) Combinational Logic Circuit 组合逻辑电路 Outputs Depend Only on its Current Inputs. ( 任何时刻的输出仅取决与当时的输入 ) Character of Circuit: No Feedback Circuit, No Memory Device ( 电路特点：无反馈回路、无记忆元件 ) Digital Logic Design and Application ( 数字逻辑设计及

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4 Basic Concepts ( 基本概念 ) Sequential Logic Circuit 时序逻辑电路 Outputs Depend Not Only on its Current Inputs, But also on the Past Sequence of Inputs. ( 任一时刻的输出不仅取决与当时的输入， 还取决于过去的输入序列 ) Character of Circuit: Have Feedback Circuit, Have Memory Device ( 电路特点：有 反馈回路 、有 记忆元件 ) Digital Logic Design and Application ( 数字逻辑设计及
5 思考：能否只用一片 1 位 全加器进行串行加法？？ C 1 S X 0 Y 0 C 0 X Y CI CO S X Y CI CO S X Y CI CO S C 0 S0 S1 Sn X0 Y0 X1 Y1 Xn Yn C1 C2 X Y CI CO S C 2 X 1 Y 1 C 1 反馈 利用反馈和时钟控制 C 3 S 2 X 2 Y 2 2 Digital Logic Design and Application ( 数字逻辑设计及

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6 暂存 X Y CI CO S C i+1 S i X i Y i C i X Y CI CO S X Y CI CO S X Y CI CO S C 0 S0 S1 Sn X0 Y0 X1 Y1 Xn Yn C1 C1 时钟控制 需要具有 记忆 功能 的逻辑单元，能够 暂存运算结果。 利用 反馈 和时钟控制 Digital Logic Design and Application ( 数字逻辑设计及
7 7.1 Bistable Elements ( 双稳态 元件 ) Q Q_L 1 1 0 0 Q Q_L It has Two Stable State : Q = 1 ( HIGH ) and Q = ( 电路有两种 稳定状态 Q = 1 ( 1 态 ) 和 Q = 0 ( —— Bistable Circuit （双稳电路 0 0 1 1 Digital Logic Design and Application ( 数字逻辑设计及

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8 7.1 Bistable Elements ( 双稳态 元件 ) Q Q_L 1 1 0 0 Q Q_L When Power is first Applied to the circuit, it Randomly Comes up in One State or the Other and Stays there Forever. ( 只要一接电源，电路就随机出现两种状态中的一种 并永久地保持这一状态。 ) 0 0 1 1 Digital Logic Design and Application ( 数字逻辑设计及
9 Vin1 Vout1 Vin2 Vout2 Vout2 Vin2 = Vin2 = Vout2 稳态 stable 亚稳态 metastabl Q Q_L Vin1 Vout1 Vin2 Vout2 Digital Logic Design and Application ( 数字逻辑设计及

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10 Metastable Behavior ( 亚稳态特性 )
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• Spring '14
• JiangChaoshu

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