第八章(3).ppt - Digital Logic Design and Application...

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1 Chapter 8 Sequential Logic Design Practices ( 时序逻辑设计实践 ) SSI Latches and Flip-Flops (SSI 型锁存器和触发器 ) MSI Device: Counters, Shift Registers (MSI 器件:计数器、移位寄存器 ) Others: Documents, Iterative, Failure and Metastability ( 其它:文档、迭代、故障和亚稳定性 ) Digital Logic Design and Application ( 数字逻辑设计及
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2 Shift Register ( 移位寄存器 ) 移位寄存器结构 串入串出、串入并出、并入串出、并入并出 MSI 移位寄存器 串入并出 74x164 、并入串出 74x166 通用移位寄存器 74x194 74x299 移位寄存器的应用 用作计数器、序列发生器 进行串 / 并转换 Digital Logic Design and Application ( 数字逻辑设计及
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3 Use an Universal Register to perform a Ring Counter( 利用通用寄存器 74 x194 实现环 形计数器 ) Q0 Q1 Q2 Q3 1 0 CLOCK Q0 Q1 Q2 Q3 1 0 1 0 0 0 RESET ( 载入 ) Q0 Q1 Q2 Q3 CLOCK Self-Correcti ( 自校正的 )
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4 Twisted-Ring Counters 扭环计数 D Q CK Q D Q CK Q D Q CK Q D Q CK Q CLK FF0 FF1 FF2 FF3 D 0 = Q n-1 0000 1000 1100 1110 1111 0111 0011 0001 无效 Normal State Cycle ( 有效的状态 Digital Logic Design and Application ( 数字逻辑设计及 Self-correcting( 自校正) Johnson, Moebius Counter
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5 Twisted-Ring Counters ( 扭环计数器 ) : 最简单的实现 D 0 = Q’ n-1 D Q CK Q D Q CK Q D Q CK Q D Q CK Q CLK FF0 FF1 FF2 FF3 1001 0100 1010 1101 0110 1011 0101 0010 0000 1000 1100 1110 1111 0111 0011 0001 Normal State ( 有效 状态 ) Abnorm State ( 无效 状态 ) 如何得到自校正 的扭环计数器? Digital Logic Design and Application ( 数字逻辑设计及
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6 Twisted-Ring Counters ( 扭环计数器 ) : 左移 LIN = Q A
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7 d d d d d d d d Minimal Cost ( 最小成本 ) Self-Correcting Design ( 自校正设 ) 1 、确定有效的状态循环 2 、对无效状态进行处理, 使其进入有效循环。 Q0 Q1 Q2 Q3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Q0Q1 00 01 11 10 00 01 11 10 Q2Q3 D0 1 0000 1000 1100 1110 1111 0111 0011 0001 1001 0100 1010 1101 0110 1011 0101 0010 1 D0 = Q3’ + Q2’·Q1 Digital Logic Design and Application ( 数字逻辑设计及
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8 = ( (Q2’·Q1)’ · Q3)’ D0 = Q3’ + Q2’·Q1 4-Bit 8-State Self-Correcting Johnson Counter(4 位 8 状态自校正的 Johnson 计数器 ) Digital Logic Design and Application ( 数字逻辑设计及
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9 利用通用寄存器 74 x194 实现扭环计数 CLK CLR S1 S0 LIN D QD C QC B QB A QA RIN 74x194 +5 V CLOCK RESET_L S1S0 接成左移形式 自校正改进: (法一) D0 = Q3’ + Q2’·Q1 Q0 Q1 Q2 Q3 Digital Logic Design and Application ( 数字逻辑设计及
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10 利用通用寄存器 74 x194 实现扭环计数 自校正改进: (法二)利用置数 每当电路输出 Q3Q2Q1Q0 出现 0XX0 时,下一状态就是 0001 D0 = Q3’+Q0’ Digital Logic Design and Application ( 数字逻辑设计及 1001 0100 1010 1101 0110 1011 0101 0010 0000 1000 1100 1110 1111 0111 0011 0001 Q0 Q1 Q2 Q3
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11 Sequence Pulse Generator ( 顺序脉冲发生器 ) 利用移位寄存器构成 — 注意自校正(环形计数器 图 8-43
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