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第六章(4).ppt - Digital Logic Design and Application...

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1 Chapter 6 Combinational Logic Design Practices ( 组合逻辑设计实践 ) Documentation Standard and Circuit Timing ( 文档标准和电路定时 ) Commonly Used MSI Combinational Logic Device ( 常用的中规模组合逻辑器件 ) Digital Logic Design and Application ( 数字逻辑设计及
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2 Decoder ( 译码器 ) Encoder ( 编码器 ) 三态器件 多路复用器 ( 优先编码器的级联和应用 ) Review of Last Class ( 内容回 ) Cascading Priority Encoders Digital Logic Design and Application ( 数字逻辑设计及
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3 译码器 编码器 Three-State Device ( 三态器件 ) Multiplexer ( 多路复用器 ) 允许多个信号驱动“同线” 实现数据双向传送 数据总线的表示法 Review of Last Class ( 内容回 ) Digital Logic Design and Application ( 数字逻辑设计及
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4 译码器 编码器 三态器件 多路复用器 EN SEL D0 Dn-1 Y 使能 选择 n b 位数据源 数据输出 b 位) 1 0 n i i i D m EN Y 标准 MSI 多路复用器 74x151 74x153 74x157 扩展多路复用器 Review of Last Class ( 内容回 ) Digital Logic Design and Application ( 数字逻辑设计及
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5 1 0 n i i i D m EN Y 当使能端有效时, 1 0 n i i i D m Y 最小项之和形式 EN A B C D0 D1 D2 D3 D4 D5 D6 D7 Y Y 74x151 实现逻辑函数 F = (A,B,C) (0,1,3,7) C B A V CC F 用多路复用器设计组合逻辑电路 Digital Logic Design and Application ( 数字逻辑设计及
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6 YZ WX 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 Y WX 00 01 11 10 0 1 1 0 Z Z Z Z Z’ 0 思考:利用 74 x151 实现逻辑函数 F = (W,X,Y,Z) (0,1,3,7,9,13,14) 降维:由 4 维 3 维 Digital Logic Design and Application ( 数字逻辑设计及 Y WX 00 01 11 10 0 1 D0 D2 D4 D1 D6 D7 D3 D5 F F F
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7 EN A B C D0 D1 D2 D3 D4 D5 D6 D7 Y Y 74x151 V CC Y X W F Z 利用 74 x151 实现 F = (W,X,Y,Z) (0,1,3,7,9,13,14) 0 2 6 4 1 3 7 5 Y WX 00 01 11 10 0 1 1 0 Z Z Z Z Z’ 0 说明:用具有 n 位地 址输入端的多路复用 器,可以产生任何形 式的输入变量数不大 n+1 的组合逻辑函 数。 Digital Logic Design and Application ( 数字逻辑设计及
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8 Example 8 1 数据选择器实现逻辑函数 F ( A , B , C , D,E ) = ∑ m (0,1,3, 9,11,12,13,14,20,21,22,23,26,31) 作函数的卡诺图和降维卡诺图。 1 0 0 0 0 0 1 0 00 01 11 10 00 01 CD AB 0 1 0 1 0 1 0 1 11 10 (a) 卡诺图 1 1 0 0 1 1 0 0 00 01 11 10 00 01 CD AB 0 0 1 1 0 1 0 1 11 10 E = 0 E = 1 1 E 0 0 E 0 00 01 11 10 00 01 CD AB 0 1 0 1 0 1 11 10 (b) 4 变量降维图 D + E E 0 0 D+E DE 1 00 01 11 10 0 1 AB C (c) 3 变量降维图 C ( D + E ) C CE+C ( D+E ) 0 1 0 1 A B (d) 2 变量降维图 E E E E DE CDE+CDE
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9 Demultiplexer (多路分配器 Route the bus data to one of m destinations ( 把输入数据送到 m 个目的地之一 ) 多路 复用器 SRCA SRCB SRCZ 多路 分配器 BUS DSTA DSTB DSTZ SRCSEL DSTSEL DST : destination SRC : source SEL : select Digital Logic Design and Application ( 数字逻辑设计及
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10 A binary decoder with an enable input can be used as a demultiplexer ( 利用带使能端的二进制译码器作为多路分配 ) A B C G1 G2A G2B Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 74 x138 DST0_L DST7_L 数据输入 SRC EN_L DSTSEL0
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