第八章(1).ppt - Digital Logic Design and Application...

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1 Clocked Synchronous State Machine Analysis ( 时钟同步状态机分 ) 由电路图确定 激励方程 输出方程 (组合电路) 将激励方程代入触发器特征方程得下一状态 Q* —— 状态方程( 转移方程 ),时序的 利用状态转移方程、输出方程构造 状态 / 输出表 画出状态图、波形图(可选) 检查电路是否可以自启动 描述电路功能 Digital Logic Design and Application ( 数字逻辑设计及
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2 Clocked Synchronous State Machine Design ( 时钟同步状态机设 ) 根据命题构造状态 / 输出表 状态化简(状态最小化) 状态编码(状态赋值) 建立转移 / 输出表(考虑未用状态的处理) 选择触发器作为状态存储器 得到激励方程和输出方程 画逻辑电路图 Digital Logic Design and Application ( 数字逻辑设计及
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3 Chapter 8 Sequential Logic Design Practices ( 时序逻辑设计实践 ) SSI Latches and Flip-Flops (SSI 型锁存器和触发器 ) MSI Device: Counters, Shift Registers (MSI 器件:计数器、移位寄存器 ) Others: Documents, Iterative, Failure and Metastability ( 其它:文档、迭代、故障和亚稳定性 ) Digital Logic Design and Application ( 数字逻辑设计及
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4 8.1 Sequential-Circuit Documentation Standards ( 时序电 路文档标准 ) General Requirements ( 一般要求 ) P479 Logic Symbols ( 逻辑符号 ) Edge-Triggered, Master/Slave Output ( 边沿触发、主从输出 ) Asynchronous Preset (at the Top) and Clear (at the Bottom) ( 异步预置(顶端)、异步清零(底端) ) Digital Logic Design and Application ( 数字逻辑设计及
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5 8.1 Sequential-Circuit Documentation Standards ( 时序电 路文档标准 ) State-Machine Description ( 状态机描述 ) Word descriptions, State tables, State Diagrams, Transition Lists ( 文字、状态表、状态图、状态转移列表 ) Timing Diagrams and Specifications ( 时序图及其规范( P682 ) Digital Logic Design and Application ( 数字逻辑设计及
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6 CLOCK H t L t clk t 触发器输出 ffpd t comb t 组合电路输出 触发器输入 hold t setup t 建立时间容限 setup comb(max) (max) ffpd clk t t t t 保持时间容限 hold comb(min) ) min ( ffpd t t t
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7 8.2 Latches and Flip-Flops ( 锁存器和触发器 ) SSI Latches and Flip-Flops 1Q 1Q 2Q 2Q 3Q 3Q 4Q 4Q 1,2 C 1D 2D 3,4C 3D 4D 74 x375 D Latches PR D Q CLK Q CLR 74 x74 PR J Q CLK K Q CLR 74 x109 PR J Q CLK K Q CLR 74 x112 P687 图 8-3 引脚 Digital Logic Design and Application ( 数字逻辑设计及
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8 Switch Debouncing ( 开关消 ) +5 V SW_L DSW Push
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