CO-2 PPT(asic).pptx - CO-2LOGIC SYNTHESIS Verilog and logic...

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CO-2 LOGIC SYNTHESIS
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Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan test - fault simulation - automatic test pattern generation.
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Verilog and Logic Synthesis A top-down design approach using Verilog begins with a single module at the top of the hierarchy to model the input and output response of the ASIC: module MyChip_ASIC(); ... (code to model ASIC I/O) ... endmodule ; This top-level Verilog module is used to simulate the ASIC I/O connections and any bus I/O during the earliest stages of design. Often the reason that designs fail is lack of attention to the connection between the ASIC and the rest of the system. As a designer, you proceed down through the hierarchy as you add lower-level modules to the top-level Verilog module
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Initially the lower-level modules are just empty placeholders, or stubs , containing a minimum of code. For example, you might start by using inverters just to connect inputs directly to the outputs. You expand these stubs before moving down to the next level of modules. module MyChip_ASIC() // behavioral "always", etc. ... SecondLevelStub1 port mapping SecondLevelStub2 port mapping ... endmodule module SecondLevelStub1() ... assign Output1 = ~Input1; endmodule module SecondLevelStub2() ... assign Output2 = ~Input2; endmodule Eventually the Verilog modules will correspond to the various component pieces of the ASIC.
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Verilog Modeling Before we could start synthesis of the Viterbi decoder we had to alter the model for the D flip-flop. This was because the original flip-flop model contained syntax (multiple wait statements in an always statement) that was acceptable to the simulation tool but not by the synthesis tool. However, finding ourselves with non-synthesizable code arises frequently in logic synthesis. The original OVI LRM included a synthesis policy , a set of guidelines that outline which parts of the Verilog language a synthesis tool should support and which parts are optional. There is no current standard on which parts of an HDL (either Verilog or VHDL) a synthesis tool should support.
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module df(D,Q,Clock,Reset); // N.B. reset is active-low output Q; input D,Clock,Reset; parameter CARDINALITY = 1; reg [CARDINALITY-1:0] Q; wire [CARDINALITY-1:0] D; always @( posedge Clock) if (Reset!==0) #1 Q=D; always begin wait (Reset==0); Q=0; wait (Reset==1); end endmodule D FLIP-FLOP
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D FLIP-FLOP - MODEFIED module df(D, Q, Clk, Rst); // new flip-flop for Viterbi decoder parameter width = 1, reset_value = 0; input [width - 1 : 0] D; output [width - 1 : 0] Q; reg [width - 1 : 0] Q; input Clk, Rst; initial Q <= {width{1'bx}}; always @ ( posedge Clk or negedge Rst ) if ( Rst == 0 ) Q <= #1 reset_value; else Q <= #1 D; endmodule
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It is essential that the structural model created by a synthesis tool is functionally identical , or functionally equivalent , to your behavioral model.
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  • Fall '15
  • prasad
  • Logic, Electronic design automation, ASIC

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