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Unformatted text preview: EEE241 Digital Logic Design (Version No.1) COMSATS Institute of Information Technology EEE241 Digital Logic Design DEPARTMENT OF ELECTRICAL ENGINEERING Prepared By: Checked By: Approved By: ----------------------------------- ----------------------------------- ----------------------------------- COMSATS Institute of Information Technology Page 1 EEE241 Digital Logic Design (Version No.1) COMSATS Institute of Information Technology EEE241 Digital Logic Design DEPARTMENT OF ELECTRICAL ENGINEERING COMSATS Institute of Information Technology Page 2 EEE241 Digital Logic Design (Version No.1) Digital Logic Design Course code: EEE241 (3+1) Prerequisites: MTH101 Calculus‐I, CSC141 Introduction to Computer Programming, EEE121 Electric Circuit Analysis‐I. Co requisites: EEE231 Electronics‐I Course Catalog Description: Introduction to Digital Computer and Systems, Number Systems, Binary Arithmetic, Boolean Algebra, Algebraic Manipulation, Canonical and Standard Form & Conversions, Logical Operations and Gates, Simplification of Functions, Karnaugh Map Methods, Two Level Implementations, Don’t Care Conditions, Prime Implicants,Combinational Logic Design, Arithmetic Operations and Circuits, Analysis Procedures, Multilevel NAND/NOR Circuits, Decoders, Encoders, Multiplexers, Demultiplexers, Memory Types, Read Only Memory, Random Access Memory, Programmable Logic Array (PLA), Sequential Logic, Flip‐Flops, Clocked Sequential Circuits, State Machine Concept, Design of Sequential Circuits using State Machines, Counters and their design, Synchronous Counters, Asynchronous Counters, Shift Registers. Textbooks: 1. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, Third Edition,McGraw‐Hill, 2013. 2. M. Morris Mano and Michael D. Ciletti,Digital Design: With an Introduction to VerilogHDL, FifthEdition, Prentice Hall, 2012. Reference Books: 1. Floyd and Jain,Digital Fundamentals,Tenth Edition, Prentice Hall, 2009. 2. Samir Palnitkar, VerilogHDL, Second Edition, Prentice Hall, 2003. Course Learning Objectives: This course aims to familiarize the students with the basic concepts in digital logic design. Two basic categories are emphasized: combinational and sequential logic circuits. The teaching material helps the students to solve many practical hardware problems and to be able to understand the principles of digital hardware design. COMSATS Institute of Information Technology Page 3 EEE241 Digital Logic Design (Version No.1) Course Learning Outcomes: After successfully completing the course, the students will be able to: 1. Apply knowledge of number systems, codes and Boolean algebra to the analysis and design of digital logic circuits. (C1‐PLO1) 2. Demonstrate an understanding of how a digital function behaves. (C2‐PLO1) 3. Analyze and synthesize logic circuits using traditional techniques (such as K‐maps and state tables). (C3‐PLO1) 4. Simulate and implement combinational and synchronous sequential circuits. (C4‐PLO2) 5. Use modern synthesis tools, such as Modelsim and Xilinx ISE, for implementing a digital circuit using Verilog and design in FPGA devices. (P3‐PLO5) Course Schedule: 3 credit hours/week One laboratory session/week (3 hours/session) Topics Covered: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Fundamental digital concepts, Boolean algebra (1 week) Number Systems and codes, synthesis using logic gates (1week) Fundamentals of Verilog, NMOS/CMOS implementation technologies (1 week) Optimized Implementation of logic functions using K‐Maps (1 week) Combinational building blocks (1.5 weeks) Arithmetic with Verilog (1 week) Verilog for combinational logic (1 week) Sequential circuits and flip‐Flops (1 week) Analysis of sequential circuits (1 week) Sequential circuit design and state machines (1.5 weeks) Synthesis using D‐flip flops, J/K and T flip‐flops (1 week) Registers and Counters (2 weeks) Introduction to RAM, ROM, PLAs, PALs and FPGAs (1 week) Assessment Plan: Theory Quizzes(4) 15% Homework assignments 10% 2 Sessional exams (in class, 60‐80 minutes each, 10%+15%) 25% Terminal exam (3 hours) 50% Total (theory) 100% Lab work Lab reports (12) 25% 2 Lab sessionals 25% Lab project and terminal exam 50% COMSATS Institute of Information Technology Total (lab) 100% Page 4 EEE241 Digital Logic Design (Version No.1) Final marks Theory marks * 0.75 + Lab marks * 0.25 Learning Outcomes Assessment Plan (Tentative): Sr. # 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Course Learning Outcomes Assessment Quiz 1 Quiz 2 Quiz 3 Quiz 4 Assignment 1 Assignment 2 Assignment 3 Assignment 4 Sessional 1 Sessional 2 Terminal Table 1 ‐ Assessment Plan for Course Learning Outcomes LaboratoryExperiences: There is a Laboratory component in all 3+1 credit courses taught at the department. Lab work consists of a minimum of 12 experiments and related assignments, which constitute 25% of the overall course‐ grade. The laboratory experiments include implementation of combinational and sequential circuits taught in class using software tools such as Modelsim and Xilinx ISE as well as 7400 series ICs. Laboratory Resources: The relevant laboratory is equipped with workbenches and computers to facilitate the experiments outlined in the lab handbook(s) that are periodically updated. A current list of the 12 lab experiments performed in this course is provided as Annexure‐II. The list of software and equipment available is also posted in all labs and is managed by staff dedicated for this purpose. Computer Resources: For the purposes of this course,the digital design and simulation softwares such as Modelsim and Xilinx ISE are installed in the laboratory that is used for implementation of digital circuits. COMSATS Institute of Information Technology Page 5 EEE241 Digital Logic Design (Version No.1) Mapping Course Learning Outcomes (CLOs) to Program Learning Outcomes (PLOs): Program Learning Outcomes: PLO 1 PLO 2 PLO 3 PLO 4 PLO 5 PLO 6 PLO 7 PLO 8 PLO 9 PLO 10 PLO 11 PLO 12 Demonstrate fundamental knowledge of mathematics, sciences and engineering related to the field of electrical and telecommunication engineering (Engineering Knowledge). Use first principles of mathematics, natural sciences, and engineering sciences to identify, formulate and analyze complex engineering problems within the domain of electrical and telecommunication engineering (Problem Analysis). Design components or processes within an engineering system according to given technical specifications while giving due consideration to safety and environmental issues (Design/Development). Investigate engineering problems through literature survey, design and execution of experiments followed by analysis and interpretation of data (Investigation). Apply appropriate techniques and modern software tools to model engineering systems and have an appreciation of the limitations and assumptions of these techniques (Modern Tool Usage). Be aware of social and safety related responsibilities in the practice of the engineering profession (Engineer and Society) Appreciate the importance of environmental sustainability issues in devising solutions to engineering problems (Environment and Sustainability) Be committed to ethical principles in the practice of the engineering profession (Ethics). Work effectively both as an individual and as a team‐member (Individual and Team Work). Demonstrate effective oral and written communication skills (Communication). Demonstrate fundamental knowledge and skills relevant to project management (Project Management) Recognize the importance of life‐long learning for professional development and be committed to pursue the latter (Lifelong Learning). PLO 10 PLO 11 CLO 2 C2 CLO 3 C3 CLO 4 C4 CLO 5 P5 PLO 9 PLO 8 PLO 7 PLO 6 PLO 4 C1 PLO 5 PLO 3 CLO 1 CLOs PLO 1 PLO 2 PLOs PLO 12 COMSATS Institute of Information Technology Page 6 EEE241 Digital Logic Design (Version No.1) Outcome Coverage Explanation: PLO 1: Demonstrate fundamental knowledge of mathematics, sciences and engineering related to the field of electrical and telecommunication engineering (Engineering Knowledge). The homework, exams, and laboratory experiments require direct application of mathematics, scientific, and engineering knowledge to successfully complete the course. This includes the function minimization using Boolean algebra, K‐Maps and state tables. (High relevance to course) PLO 2: Use first principles of mathematics, natural sciences, and engineering sciences to identify, formulate and analyze complex engineering problems within the domain of electrical and telecommunication engineering (Problem Analysis). The final design project is given as a set of specifications that the students' design must meet. Therefore, they must identify the key limiting issues, formulate a solution strategy, research and test their approach, and finally prototype and test the design to prove that it works. (High relevance to course) PLO 3: Design components or processes within an engineering system according to given technical specifications while giving due consideration to safety and environmental issues (Design/Development). Approximately one half of the homework problems are design oriented, requiring the students to design a digital circuit to accomplish a given specification. The laboratory concludes with a comprehensive, open‐ended design project in which the students apply the material that they have been exposed to during the semester to design, prototype, and test a small digital system. (Medium relevance to course) PLO 4: Investigate engineering problems through literature survey, design and execution of experiments followed by analysis and interpretation of data (Investigation). Students conduct some pre‐designed experiments in the laboratory sessions.However, they also design and simulate a digital circuit starting from a design specification assigned to them in the laboratory.(Medium relevance to course) PLO 5: Apply appropriate techniques and modern software tools to model engineering systems and have an appreciation of the limitations and assumptions of these techniques (Modern Tool Usage). Various simulation and design tools are used in the laboratory to give students hands‐on experience. (Medium relevance to course) PLO 9: Work effectively both as an individual and as a team‐member (Individual and Team Work). The course project to be done in teams imparts the ability to function on teams as well as honing on time management skills. As an experiment a cross‐departmental team can be established to work on a larger project that requires HW and SW skills. (Low relevance to course) PLO 11: Demonstrate fundamental knowledge and skills relevant to project management (Project Management) The course project to be done imparts the ability to plan and manage the project keeping in view the available resources, cost and time. This activity helps students to go through the life cycle of project planning and management. As an experiment a cross‐departmental team can be COMSATS Institute of Information Technology Page 7 EEE241 Digital Logic Design (Version No.1) established to work on a larger project that requires hardware and software skills. (Low relevance to course) PLO 12: Recognize the importance of life‐long learning for professional development and be committed to pursue the latter (Lifelong Learning).The ability to design, simulate and implement digital circuits that can be used for continued learning throughout a lifetime in related disciplines.(High relevance to course) COMSATS Institute of Information Technology Page 8 EEE241 Digital Logic Design (Version No.1) ANNEXURE‐I Tentative Lecture Breakdown (30 Lectures): Topics Introduction to Digital Systems, binary numbers, and Number base conversions, Binaryarithmetic operations, Complements of numbers, and subtraction with compliments, BinaryLogic, Theorems and Postulates of Boolean Algebra, Operator Precedence Digital Logic Gates , Logic Levels, Boolean functions, (NAND‐NOR Implementation), Algebraic Manipulation, Function Complement, Canonical and Standard Forms, SignedBinary Numbers K‐Maps, Prime Implicants, Essential Prime Implicants, Product of Sum Simplification andDon’t care Conditions Combinational Logic: Analysis Procedure and Design Procedure, Binary Adder/Subtractor,BCD Adder, Binary Multiplier, Magnitude Comparator and Decoders, Encoders, ParityEncoders, Mux, Boolean Function Implementation using MUX Sequential Circuits, SR Latch (NAND/NOR), D Latch, Types and characteristics of FlipFlops (D, J‐K, T), Analysis of clocked Sequential circuits (State Equations, State Table, StateDiagram) Mealay and Moore models of Finite State Machines, State reductions and State Assignments,Design Procedure of Sequential Circuits, Synthesis using D‐F/F (Sequence Detector Non‐Overlapping), Excitation Tables, Pattern/Sequence Detector (Overlapping), Synthesis usingJ/K, T F/F Registers, Register with Parallel Load, Shift Registers, Universal Shift Register Binary Ripple Counter, Synchronous Counter (Binary Counter), Up/Down Binary Counter Introduction to Memory, RAM, ROM, PLDs, PALs and FPGAs No. of Lectures 3 3 2 7 4 5 2 2 2 COMSATS Institute of Information Technology Page 9 EEE241 Digital Logic Design (Version No.1) ANNEXURE‐II List of Experiments: Lab No. 1 2 3 4 5 6 7 8 9 10 11 12 13‐14 Details Introduction to Proteus and basic logic gate ICs on KL‐31001 trainer. Boolean function and universal gates implementation on KL‐31001 trainer using gate ICs. Introduction to structured Verilog and test benches using ModelSim. Boolean function implementation/design using SOP and POS forms by using ICs/Verilog. Logic minimization of large functions using automated tools. Logic minimization of large functions using automated tools. Design of n‐bit adder/subtractor using Verilog. Implementation of binary to BCD to 7‐segment decoder on FPGA. Implementation of binary multiplier on FPGA. Design and implementation of practical example using encoder and multiplexer. Moore machine implementation of counter/ Mealy machine implementation of sequence detector. Universal shift register/LFSR on FPGA. Lab Project / Viva COMSATS Institute of Information Technology Page 10 ...
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