EE 306 - Appendix A - appendix a The LC-3 ISA A.1 Overview...

appendix a
TheLC-3ISA
A.1 Overview
The Instruction Set Architecture (ISA) of the LC-3 is defined as follows:
Memory address space 16 bits, corresponding to 2
16
locations, each
containing one word (16 bits). Addresses are numbered from 0 (i.e, x0000)
to 65,535 (i.e., xFFFF). Addresses are used to identify memory locations
and memory-mapped I/O device registers. Certain regions of memory are
reserved for special uses, as described in Figure A.1.
Bit numbering Bits of all quantities are numbered, from right to left,
starting with bit 0. The leftmost bit of the contents of a memory location is
bit 15.
Instructions Instructions are 16 bits wide. Bits [15:12] specify the opcode
(operation to be performed), bits [11:0] provide further information that is
x0000
Interrupt Vector Table
x01FF
x0200
x2FFF
x3000
xFDFF
xFE00
xFFFF
Trap Vector Table
Device register addresses
Operating system and
Supervisor Stack
Available for
user programs
x00FF
x0100
Figure A.1
Memory map of the LC-3

522 appendix a The LC-3 ISA
needed to execute the instruction. The specific operation of each LC-3
instruction is described in Section A.3.
Illegal opcode exception Bits [15:12] = 1101 has not been specified. If an
instruction contains 1101 in bits [15:12], an illegal opcode exception
occurs. Section A.4 explains what happens.
Program counter A 16-bit register containing the address of the next
instruction to be processed.
General purpose registers Eight 16-bit registers, numbered from 000 to
111.
Condition codes Three 1-bit registers: N (negative), Z (zero), and P
(positive). Load instructions (LD, LDI, LDR, and LEA) and operate
instructions (ADD, AND, and NOT) each load a result into one of the eight
general purpose registers. The condition codes are set, based on whether
that result, taken as a 16-bit 2’s complement integer, is negative
( N = 1 ; Z , P = 0 ) , zero ( Z = 1 ; N , P = 0 ) , or positive ( P = 1 ; N , Z = 0 ) .
All other LC-3 instructions leave the condition codes unchanged.
Memory-mapped I/O Input and output are handled by load/store
(LDI/STI, LDR/STR) instructions using memory addresses to designate
each I/O device register. Addresses xFE00 through xFFFF have been
allocated to represent the addresses of I/O devices. See Figure A.1. Also,
Table A.3 lists each of the relevant device registers that have been identified
for the LC-3 thus far, along with their corresponding assigned addresses
from the memory address space.
Interrupt processing I/O devices have the capability of interrupting the
processor. Section A.4 describes the mechanism.
Priority level The LC-3 supports eight levels of priority. Priority level 7
(PL7) is the highest; PL0 is the lowest. The priority level of the currently
executing process is specified in bits PSR[10:8].
Processor status register (PSR) A 16-bit register, containing status
information about the currently executing process. Seven bits of the PSR
have been defined thus far. PSR[15] specifies the privilege mode of
the executing process. PSR[10:8] specifies the priority level of the currently
executing process. PSR[2:0] contains the condition codes. PSR[2] is N,
PSR[1] is Z, and PSR[0] is P.