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EECS270-W09-EXAM02-solutions

# EECS270-W09-EXAM02-solutions - The University of Michigan...

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1 The University of Michigan EECS 270: Introduction to Logic Design Winter 2009 Exam 2 Solutions Professor Valeria Bertacco Professor Kang. G. Shin Wednesday March 25, 2009 7:00 to 8:30 pm Name: ________________________________ UMID: ________________________________ Honor Pledge: “I have neither given nor received aid on this exam, nor have I concealed any violations of the Honor Code.” Signature: ____________________________ 1: _______ / 12 2: _______ / 14 3: _______ / 12 4: _______ / 16 5: _______ / 14 6: _______ / 20 7: _______ / 12 Total : ______ /100 EC: ______ / 15 Instructions The exam is closed book . No books, notes or the like may be used. No computers, calculators, PDAs, cell phones or other electronic devices may be used Print your name, give your UMID, and sign the Honor Pledge above when you are done. Show all your work . You get partial credit for partial answers. The exam consists of seven regular and one extra credit problems with the point distribution indicated on the right. Please keep this in mind as you work

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2 Problem 1 : [ Two’s Complement Addition/Subtraction : 12 points] You are asked to perform -8-9 with the following 5-bit 2’s complement adder/subtracter. What are the values of A, B, BI, Sel, Cin, Sum, and Cout? Write your answers in binary below. A __11000___ B __01001 / 10111 Cout __ 1 _______ BI __10110 / 10111 Sum __ 01111 ____ Sel __1 / 0_______ Does overflow occur? Cin __1 / 0_______ Y / N
3 Problem 2 [ Counters : 14 points] Binary-coded decimal ( BCD ) is an encoding for decimal numbers in which each decimal digit (0,1,2…9) is represented by its own binary sequence. Each decimal digit is represented with a set of 4 bits – keep in mind that only the binary symbols from 0000 to 1001 are legal in BCD. For example, the decimal number 43 in BCD encoding will be represented as 0100 0011, not as 101011. Design a BCD counter that will count up from 13 to 99. At the positive clock edge, if the reset is low, the counter will start its count up from 13 and wrap around when it reaches 99. Use the 4-bit up counters shown below. They have a synchronous load (LD), a synchronous clear (CLR) and an active low chip enable (CEN). LD and CLR are both active high. Complete the following design using as few logic gates as possible. You are allowed to only use 2-input NAND gates

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4 Problem 3 : [ Counters and Shift Registers : 12 points] Consider the design below, constructed with one up-counter and one left-shift register. Let outputs out3-out0 be the binary representation of a number x between 0 and 15 (out3 is the MSB). What is the repeating sequence of decimal numbers this design will produce on out 3 -out 0 ? Hint: Assume the counter starts in state Q2,Q1,Q0 = 000 Counter . Q2 Q1 Q0 Ld Sh_in out3 out2 out1 out0 out3-out0 (decimal) 0 0 0 1 x x x x x x 0 0 1 0 1 1 0 0 1 9 0 1 0 1 0 0 0 1 1 3 0 1 1 0 0 1 0 1 1 11 1 0 0 0 1 0 1 1 0 6 1 0 1 1 1 1 1 0 1 13 1 1 0 0 0 1 1 0 0 12 1 1 1 1 0 1 0 0 0 8 0 0 0 1 1 1 1 1 0 14
5 Problem 4 : [ Datapath Design 2 : 16 points] In mathematics, a prime number is a natural number which has exactly two distinct natural number divisors: 1 and itself. Note that 1 is NOT a prime number.

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