The University of Texas at Austin
EE 306, Fall 2006
Problem Set 2
Solutions
Due: 20 September, before class
22 September, before discussion section
Yale N. Patt, Instructor
TAs: Aseem Bathla, Cameron Davison, Lisa de la Fuente, Phillip Duran, Jose Joao,
Jasveen Kaur, Rustam Miftakhutdinov, Veynu Narasiman, Nady Obeid, Poorna
Samanta
Instructions:
You are encouraged to work on the problem set in groups and turn in one problem set for
the entire group. Remember to put all your names on the solution sheet. Also, remember
to put the name of the TA and the time for the discussion section you would like the
problem set turned back to you. Show your work.
1.
(5 pts)
(Adapted from 2.37 in textbook, and from Problem Set 1)
Two 4bit 2's complement numbers, n and m, are added, yielding s, the 4bit
result. Determine, using only the AND, OR, and NOT logical operations, if an
overflow has occurred during the addition? Construct a logic circuit that does this.
The inputs to the logic circuit are n[3:0], m[3:0], and s[3:0]. The output is 0 if no
overflow occurs and 1 if an overflow does occur.
2.
(5 pts)
(2.54, and from Problem Set 1)
Fill in the truth table for the equations given. The first line is done as an example.
We have intentionally left several blank output columns for you to use as you
wish.
Q1 = NOT (NOT(X) OR (X AND Y AND Z))
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 Fall '06
 MCCANN
 Electrical Engineering, pts, Logic gate, Department of Electrical and Computer Engineering, logic circuit

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