problemset3solutions - Department of Electrical and...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
Department of Electrical and Computer Engineering The University of Texas at Austin EE 306, Fall 2006 Problem Set 3 Solutions Yale N. Patt, Instructor TAs: Aseem Bathla, Cameron Davison, Lisa de la Fuente, Phillip Duran, Jose Joao, Jasveen Kaur, Rustam Miftakhutdinov, Veynu Narasiman, Nady Obeid, Poorna Samanta Questions and Answers 1. (3.28) (18 points: 2 for a-d, 5 for e-f) Having designed a binary adder, you are now ready to design a 2-bit by 2-bit unsigned binary multiplier. The multiplier takes two 2-bit inputs A[1:0] and B[1:0] and produces an output Y which is the product of A[1:0] and B[1:0] . The standard notation for this is: Y = A[1:0] B[1:0] a. What is the maximum value that can be represented in 2 bits for A[1:0] ? 3 b. What is the maximum value that can be represented in 2 bits for B[1:0] ? 3 c. What is the maximum possible value of Y ? 9 = 3×3 d. What is the number of required bits to represent the maximum value of Y ? 4 bits, since 2 3 -1= 7 is not enough, but 2 4 -1= 15 is sufficient
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
e. Write a truth table for the multiplier described above. You will have a four input truth table with the inputs being A[1] , A[0] , B[1] , and B[0] . f. Implement the third bit of output, Y[2] from the truth table using only AND , OR , and NOT gates. (We are only asking you for one bit of output in order to reduce the amount of busy work. You should be able to do all bits of output, when asked.) 2. (3.33) (9 points: 3 for each item)
Background image of page 2
Using Figure 3.21, the diagram of the 4-entry, 2 2 -by-3-bit memory. a. To read from the fourth memory location, what must the values of A[1:0] and WE be? To read the 4th memory location, A[1,0] = 11, WE = 0 b. To change the number of entries in the memory from 4 to 60, how many address lines would be needed? What would the addressability of the memory be after this change was made? A total of 6 address lines are required for a memory with 60 locations. The
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/26/2009 for the course EE 302 taught by Professor Mccann during the Fall '06 term at University of Texas at Austin.

Page1 / 7

problemset3solutions - Department of Electrical and...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online