Unformatted text preview: 8.1 Vout (V) 5 4 3 2 1 2 1 0 0 1 2 3 4 Vin 5 (mV) 1 2 8.11 V = V+ = Vin V = R2 R4 (R2 + R3 ) Vout = Vin R1 + R4 (R2 + R3 ) R2 + R3
1 Vout R2 R4 (R2 + R3 ) = Vin R1 + R4 (R2 + R3 ) R2 + R3 = (R2 + R3 ) [R1 + R4 (R2 + R3 )] R2 [R4 (R2 + R3 )] If R1 0, we expect the result to be: Vin = Vout Vin R2 Vout R2 + R3 R2 + R3 R3 = =1+ R2 R2 R1 =0 Taking limit of the original expression as R1 0, we have: (R2 + R3 ) [R1 + R4 (R2 + R3 )] (R2 + R3 ) [R4 (R2 + R3 )] = R1 0 R2 [R4 (R2 + R3 )] R2 [R4 (R2 + R3 )] R3 =1+ R2 lim This agrees with the expected result. Likewise, if R3 0, we expect the result to be: Vin = Vout Vin R2 R4 Vout R1 + R2 R4 R1 + R2 R4 = R2 R4 R1 =1+ R2 R4 R3 =0 Taking the limit of the original expression as R3 0, we have: lim (R2 + R3 ) [R1 + R4 (R2 + R3 )] R2 (R1 + R2 R4 ) = R2 [R4 (R2 + R3 )] R2 (R2 R4 ) R1 + R2 R4 = R2 R4 R1 =1+ R2 R4 R3 0 This agrees with the expected result. 8.14 We need to derive the closedloop gain of the following circuit: R1 R2 + vin  + vX   + A0 vX Rout vout vX = (vout  vin ) vout R2 + vin R1 + R2 R1 + R2 + vin = (A0 vX  vin ) Rout + R1 + R2 R2 + vin  vin = A0 (vout  vin ) R1 + R2 R1 + R2 + vin Rout + R1 + R2 Grouping terms, we have: vout 1 + A0 R2 R1 + R2 = vin R1 + R2 Rout + R1 + R2 R1 + R2 R2 Rout + R1 + R2 A0  A0  1 + Rout + R1 + R2 R1 + R2 R1 + R2 R1 + R2 R1 Rout + R1 + R2 = vin  A0 1 Rout + R1 + R2 R1 + R2 R1 + R2 1 [Rout + R1 + R2  A0 R1  R1  R2 ] = vin Rout + R1 + R2 A0 R1 + R1 + R2 = vin 1  Rout + R1 + R2 R +R1 +R2 1  A0out1+R1 +R2 vout R = 2 vin 1 + RoutA0 R1 +R2 +R = = Rout + R1 + R2  A0 R1  R1  R2 Rout + R1 + R2 + A0 R2 Rout  A0 R1 Rout + R1 + (1 + A0 ) R2
vt it To find the output impedance, we must find Zout = R1 R2 + vX  for the following circuit: Rout + A0 vX  it  + vt vt vt + A0 vX + Rout R1 + R2 R2 vX = vt R1 + R2 vt + A0 R1R2 2 vt vt +R + it = Rout R1 + R2 A0 R2 1 1 + + = vt Rout Rout (R1 + R2 ) R1 + R2 R1 + (1 + A0 ) R2 + Rout = vt Rout (R1 + R2 ) it = Zout = Rout (R1 + R2 ) vt = it R1 + (1 + A0 ) R2 + Rout 8.15 Refer to the analysis for Fig. 8.42. Vout R1 = =4 Vin R2 Rin R2 = 10 k R1 = 4R2 = 40 k From Eq. (8.99), we have E =1 A0  1+
Rout R2 Rout R1 R1 R2 + A0 + A0 = 1000 Rout = 1 k E = 0.51 % 8.17 V+ = V (since A0 = ) Vin Vout R3 R4 = R2 R3 R1 + R3 R4 Vout R3 R1 + R3 R4 =  Vin R2 R3 R4 If R1 0 or R3 0, we expect the amplifier to reduce to the standard inverting amplifier. Vout Vin Vout Vin The gain reduces to the expected expressions. =
R1 0 R3 R2 R1 R2 =
R3 0 8.18 V+ = V (since A0 = ) R3 R2 VX = Vout = (Vout  Vin ) + Vin R3 + R4 R1 + R2 R3 R2 R2 Vout = Vin 1   R3 + R4 R1 + R2 R1 + R2 R1 R3 (R1 + R2 )  R2 (R3 + R4 ) = Vin (R1 + R2 ) (R3 + R4 ) R1 + R2 Vout R1 (R3 + R4 ) = Vin R3 (R1 + R2 )  R2 (R3 + R4 ) Vout 8.22 We must find the transfer function of the following circuit: C1 R1 + vin  Rin + vX  + A0 vX  vout vout = A0 vX vX = vout  vX 1+ 1 sRin C1 + 1 sR1 C1 vX vout vout 1 + A0 sR1 Rin C1 sR1 Rin C1 + R1 + Rin vout vin 1 vX  vin vX + sC1 Rin R1 vin = vout + sR1 C1 sR1 Rin C1 vout + Rin vin = sR1 Rin C1 + R1 + Rin sR1 Rin C1 vout + Rin vin = A0 sR1 Rin C1 + R1 + Rin Rin = A0 vin sR1 Rin C1 + R1 + Rin A0 Rin sR1 Rin C1 + R1 + Rin = sR1 Rin C1 + R1 + Rin sR1 Rin C1 + R1 + Rin + sR1 Rin C1 A0 A0 Rin = sR1 Rin C1 + R1 + Rin + sR1 Rin C1 A0 A0 Rin = sR1 Rin C1 (1 + A0 ) + R1 + Rin A0 Rin = in 1 + s R1 RR1C1 (1+A0 ) +Rin = A0 Rin / (R1 + Rin ) 1 + s (R1 Rin ) C1 (1 + A0 ) (R1 1 Rin ) C1 (1 + A0 ) Rin , sp =  Comparing this to the result in Eq. (8.37), we can see that we can simply replace R1 with R1 effectively increasing the pole frequency (since R1 Rin < R1 for finite Rin ). We can also write the result as sp =  1 R1 C1 (1 + A0 ) 1+ R1 Rin In this form, it's clear that the pole frequency increases by 1 + R1 /Rin . 8.23 We must find the transfer function of the following circuit: C1 R1 + vin  + vX   + A0 vX Rout vout vout = A0 vX + vX = vin + vin  vout 1 Rout R1 + sC1 R1 1 (vout  vin ) R1 + sC1 R1 vin  vout 1 (vout  vin ) + 1 Rout R1 + sC1 R1 + sC1 A0 R1 + Rout 1 R1 + sC1 R1 +
1 sC1 vout = A0 vin + vout 1 + vout R1 +
1 sC1 A0 R1 + Rout 1 R1 + sC1
1 sC1 = vin A0 + = vin + A0 R1 + Rout 1 A0 R1  A0 sC1 + A0 R1 + Rout R1 + vout {1 + sC1 [(1 + A0 ) R1 + Rout ]} = vin {A0  sC1 Rout } A0  sC1 Rout vout =  vin 1 + sC1 [(1 + A0 ) R1 + Rout ] sp =  1 C1 [(1 + A0 ) R1 + Rout ] Comparing this to the result in Eq. (8.37), we can see that the pole gets reduced in magnitude due to Rout . 8.26 We must find the transfer function of the following circuit: R1 C1 vout + vin  Rin + vX   + A0 vX vout = A0 vX vX = (vin  vX ) sC1  vX 1 + sRin C1 + Rin R1 vX  vout Rin R1 Rin = vin sRin C1 + vout R1 vin sRin C1 + vout Rin R1 1 + sRin C1 +
Rin R1 vX = vout = A0 vout 1 + vout A0 Rin R1 1 + sRin C1 +
Rin R1 Rin R1 Rin R1 vin sRin C1 + vout Rin R1 1 + sRin C1 +
Rin R1 = vin = vin sRin C1 A0 1 + sRin C1 + Rin R1 sRin C1 A0 1 + sRin C1 + Rin R1 1 + sRin C1 + (1 + A0 ) 1 + sRin C1 + vout 1 + sRin C1 + (1 + A0 ) Rin = vin sRin C1 A0 R1 vout sR1 Rin C1 A0 =  vin R1 + sR1 Rin C1 + (1 + A0 ) Rin vout lim = sR1 C1 A0 vin Comparing this to Eq. (8.42), we can see that if we let A0 , the result actually reduces to Eq. (8.42). 8.27 We must find the transfer function of the following circuit: R1 C1 + vin  + vX   + A0 vX Rout vout vout = A0 vX + vX = vin + vin  vout 1 Rout R1 + sC1
1 sC1 1 sC1 R1 + (vout  vin )
1 sC1 vout = A0 vin + vout 1 + vout R1 +
1 sC1 1 A0 sC1 + Rout R1 + 1 sC1 (vout  vin ) + vin  vout 1 Rout R1 + sC1 R1 +
1 sC1 1 sC1 = vin A0 + = vin 1 A0 sC1 + Rout R1 + R1 + 1 sC1 1 + A0 sC1 + Rout 1 1 A0 R1  A0 sC1 + A0 sC1 + Rout 1 sC1 R1 + vout {1 + A0 + sC1 (R1 + Rout )} = vin {sC1 (A0 R1  Rout )} vout sC1 (A0 R1  Rout ) =  vin 1 + A0 + sC1 (R1 + Rout ) vout = sR1 C1 lim A0 vin Comparing this to Eq. (8.42), we can see that if we let A0 , the result actually reduces to Eq. (8.42). 8.28 vout = A0 v v = vin + (vout  vin ) 1 sC1 1 sC1 R1
1 sC2 1 sC1 R1 + R2 R1
1 sC2 vout 1 sC1 vout 1 + A0 R1 +
1 sC1 1 sC1 1 sC1 1 sC2 R1
1 sC2 1 sC1 vout = A0 vin + (vout  vin ) R2 R1 = vin A0 1  = vin A0 = vin A0
1 sC1 1 sC1 R1 + R2 R1 + R2 + A0
1 sC2 1 sC1 R1
1 sC2 1 sC1 R1 +
1 sC2 R2 1 sC1 R1 +
1 sC1 R2 
1 sC2 R1 R1 + 1 sC1 R2 1 sC2 R2 R1 + R2 vout (1 + A0 ) R1 + 1 sC2 R2
1 sC2 1 sC1 vout = A0 vin (1 + A0 ) R2 R1 +
1 sC2 R2 Unity gain occurs when the numerator and denominator are the same (note that we can drop the negative sign since we only care about the magnitude of the gain): A0 (A0  1) 1 sC2 1 sC2
1 sC2 1 sC1 R2 R2 R2 R1 = (1 + A0 ) = (1 + A0 ) = A0 + 1 A0  1 1 sC1 1 sC1 R1 R1 + 1 sC2 R2 It is possible to obtain unity gain by choosing the resistors and capacitors according to the above formula. 8.31 vout = A0 vX v1  vX v2  vX vX  vout + = R2 R1 RF vout v1 v2 vX + + = RF R2 R1 R1 R2 RF vout = A0 (R1 vout 1 + A0 (R1 R2 RF ) = A0 (R1 RF vout = A0 (R1 R2 R2 R2 RF ) RF ) RF ) R2 vout v1 v2 + + RF R2 R1 v2 v1 + R2 R1 v1 v2 R2 + R1 1 + A0 (R1
R2 RF ) RF v1 v2 R2 + R1 = A0 RF (R1 =  v1 v2 + R2 R1 RF ) RF + A0 (R1 R2 R2 RF ) [RF A0 (R1 RF )] 8.32 For A0 = , we know that v+ = v , meaning that no current flows through RP . Thus, RP will have no effect on vout . vout = RF v1 v2 + R2 R1 , A0 = For A0 < , we have to include the effects of RP . vout = A0 vX v2  vX vout  vX v1  vX RP + + R2 R1 RF 1 v1 1 1 1 v2 vout vX = + + + + + RP R1 R2 RF R2 R1 RF v2 vout v1 (R1 R2 RF RP ) + + vX = R2 R1 RF v1 v2 vout vout = A0 (R1 R2 RF RP ) + + R2 R1 RF v1 v2 A0 (R1 R2 RF RP ) (R1 R2 RF RP ) = A0 + 1+ RF R2 R1 v1 v2 (R1 R2 RF RP ) vout = A0 + A R2 R1 1 + R 0 (R1 R2 RF RP ) F vX = = =  v1 v2 + R2 R1 v1 v2 + R2 R1 RF A0 (R1 R2 RF RP ) RF + A0 (R1 R2 RF RP ) [RF A0 (R1 R2 RF RP )] , A0 < vout 8.33 We must find vout for the following circuit: v1 R2 RF Rout R1 + vX   + A0 vX vout v2 vout = A0 vX + vX vX 1 1 1 + + RF R1 R2 vX vout v1  vX v2  vX Rout + R2 R1 v1 Rout v2 Rout + Rout + + = vX A0 + R1 R2 R2 R1 v1  vX v2  vX = vout + RF + R2 R1 vout v1 v2 = + + RF R2 R1 vout v1 v2 = (R1 R2 RF ) + + RF R2 R1 Rout v1 v2 Rout vout (R1 R2 RF ) A0 + + + + = RF R2 R1 R1 R2 + Rout v1 v2 + R2 R1 Grouping terms, we have: (R1 R2 RF ) A0 + vout 1 + RF Rout R1 R2 = v2 v1 + R2 R1 v2 v1 + R2 R1 (R1 (R1 R2 R2 RF ) A0 + Rout R1 R2 Rout R1 R2 + Rout + Rout
Rout R1 R2 Rout R1 R2 v1 v2 + R2 R1 = RF ) A0 + R2 R2 vout = RF v1 v2 + R2 R1 Rout + (R1 RF + (R1 RF ) A0 + RF ) A0 + 8.34 We must find vout for the following circuit: v1 R2 RF vout v2 R1 + Rin vX   + A0 vX RP Grouping terms, we have: vX vout = A0 vX v1  vX 1 + vX = R1 RP Rin + v2  vX 1 + R2 RP Rin + vout  vX 1 + RF RP Rin Rin 1 v1 RP v2 vout 1 = + 1+ + + Rin Rin R1 R2 RF R2 R1 RF (R1 R2 RF ) + RP + Rin v1 v2 vout vX = + + Rin (R1 R2 RF ) R2 R1 RF v2 vout Rin (R1 R2 RF ) v1 + + vX = R2 R1 RF (R1 R2 RF ) + RP + Rin v1 v2 vout Rin (R1 R2 RF ) vout = A0 + + R2 R1 RF (R1 R2 RF ) + RP + Rin Grouping terms, we have: A0 Rin (R1 R2 RF ) = RF (R1 R2 RF ) + RP + Rin R2 RF ) + RP + Rin ] + A0 Rin (R1 R2 RF ) = RF [(R1 R2 RF ) + RP + Rin ] vout 1 + v2 v1 + R2 R1 v1 v2 + R2 R1 A0 Rin (R1 R2 RF ) (R1 R2 RF ) + RP + Rin A0 Rin (R1 R2 RF ) (R1 R2 RF ) + RP + Rin vout RF [(R1 Simplifying, we have: vout =  v1 v2 + R2 R1 A0 RF Rin (R1 R2 RF ) RF ) + RP + Rin ] + A0 Rin (R1 RF [(R1 R2 R2 RF ) 8.35 ID1 = Plotting ID1 (t), we have
Vin R1 0 Vin > 0 Vin < 0 V0 V0 /R1 0 0 / 0 t / V0 Vin (t) = V0 cos(t) (Dotted) ID1 (t) 8.36 ID1 = Plotting ID1 (t), we have
Vin R1 0 Vin > 0 Vin < 0 V0 V0 /R1 0 0 / 0 t / V0 Vin (t) = V0 cos(t) (Dotted) ID1 (t) 8.37 VY = Vin  VD,on VDD Vin < 0 Vout Vin > 0 = Vin 0 Vin < 0 ID1 = Vin > 0
Vin R1 0 Vin < 0 Vin > 0 Plotting VY (t) and Vout (t), we have Vin (t) = V0 cos(t) VY (t) Vout (t) VDD V0 / 0 0 / t V0 Plotting ID1 (t), we have: ID1 (t) V0 /R1 0 / 0 t / 0 V0 V0 Vin (t) = V0 cos(t) (Dotted) 8.38 Since the negative feedback loop is never broken (even when the diode is off, RP provides negative feedback), V+ = V will always hold, meaning VX = Vin . We must determine when D1 turns on/off to determine VY . We know that for Vin < 0, the diode will be off, and VX will follow Vin . As Vin begins to go positive, the diode will remain off until Vin RP > VD,on R1 Once the diode turns on, VY will be fixed at Vin + VD,on . Thus, we can write: VX = Vin VY = Plotting VY (t) and Vout (t), we have Vin 1 +
RP R1 R1 Vin < VD,on RP R1 Vin > VD,on RP Vin + VD,on Vin (t) = V0 cos(t) VX (t) VY (t) V0 + VD,on V0 / 0 0 / t V0 V0 (1 + RP /R1 ) 8.40 Note that although in theory the output is unbounded (i.e., by Eq. (8.66), we can take the logarithm of an arbitrarily small positive number), in reality the output will be limited by the positive supply rail, as shown in the following plot. Vout VX VDD 1 0 1 0 R1 IS 1 Vin (V) 8.42 When Vin > 0, the feedback loop will be broken, and the output will go to the positive rail. When Vin < 0, we have: IC =  Vin = IS eVBE /VT = IS eVout /VT R1 Vin R1 IS Vout = VT ln  This gives us the following plot of Vout vs. Vin : Vout (V) 1 R1 IS VDD 0 0 1 Vin (V) Note that this circuit fails to behave as a noninverting logarithmic amplifier. 8.44 (a) Vout = VT ln 0.2 V = VT ln R1 IS = 456 V (b) Av = dVout dVin Vin R1 IS 1V R1 IS Vin =1 V VT = Vin Vin =1 V = 0.026 8.45 When Vin < VT H , the output goes to the positive rail. When Vin > VT H , we have: ID = Vin  VT H R1
W L VGS = Vout = VT H + 2ID n Cox Vout = VT H  1 dVout = dVin 2 =  2 (Vin  VT H ) R1 W n Cox L R1 W n Cox 2 L 2 (Vin  VT H ) R1 W n Cox L 1 , Vin > VT H 2R1 W n Cox (Vin  VT H ) L 8.46 When Vin > 0, the output goes to the negative rail. When Vin < 0, we have: ID =  Vin R1
W L VSG = Vout = VT H  + 2 ID  p Cox Vout = VT H +  2Vin , Vin < 0 R1 W p Cox L 8.49 We model an input offset with a series voltage source at one of the inputs. R1 R2
 Vout Vin +  + Vos +  Vout = Vin  = Vin =  Vin  Vos (R1 + R2 ) R2 R1 + R2 R1 + R2 + Vos 1 R2 R2 Vos R1 R1 Vin + 1 + R2 R2 Note that even when Vin = 0, Vout = (1 + R1 /R2 ) Vos . 8.54 Let Vin = 0. V+ = IB1 (R1 R2 ) =  (IB2 + I) (R1 V R2 R1 R2 ) + IB2  R2 ) 1 + R1 R2 (IB2 + I) (R1 R2 + IB2 R1 R2 ) R1 R2 ) = V Vout = V + IB2 + =  (IB2 + I) (R1 =  (IB2 + I) (R1 = IR1 If the magnitude of the error must be less than V , we have: IR1 < V R1 < Note that this does not depend on R2 . V I 8.57 Vout =  A0 s V 1 + 0 Vout  Vin 1 R1 R1 + sC1 Vin + Vout  Vin 1 R1 R1 + sC1 V = Vin + Vout =  Vout 1 + 1+ Vout
s 0 A0 s 1 + 0 A0 R1 s 1 1 + 0 R1 + sC1
1 sC1 = A0 R1 s Vin 1 1 1 + 0 R1 + sC1
1 A0 sC1 R1 +
s 0 + A0 R1
1 sC1 1+ R1 + = Vin 1+ s 0 R1 +
1 A0 sC1 1 sC1 Vout = Vin 1+ = 1+ = s 0 R1 + 1 sC1 + A0 R1 A0
s 0 (1 + sR1 C1 ) + sA0 R1 C1 A0
1 0
1 + A0 R1 C1 + s2 RC1 0 1 + s R1 C1 + =  A0 1 + s (1 + A0 ) R1 C1 +
1 0
1 + s2 RC1 0 If 0 1 R1 C1 , we have: Vout = Vin =  1
1 A0 +s 1+ 1 A0 R1 C1 + 1 0 1 + s2 R1 C0 A0 1
1 A0 +s 1+ 1 A0 1 R1 C1 + s2 R1 C0 A0 1 (assuming A0 1) 1 sR1 C1 + s2 R1 C0 A0 1 sR1 C1 1 +
s A0 0 =  8.61 Let E refer to the gain error. R1 =8 R2 R1 = 8 k R2 = 1 k A0  Rout R1 vout R1 = vin R2 1 + Rout + A0 + R
2 R1 R2 (Eq. 8.99) R1 (1  E) R2 A0  Rout R1 E =1 1 + Rout + A0 + R2 = = 0.1 % A0 = 9103 R1 R2 Note that we can pick any R1 , R2 such that their ratio is 8 (i.e., this solution is not unique). However, A0 will change depending on the values chosen. 8.66 Vout = VT ln dVout dVin Vin R1 IS R1 IS 1 = VT Vin R1 IS VT = Vin VT No, it is not possible to satisfy both requirements. As shown above, dVout = Vin , meaning for a dVin specified temperature and input, the gain is fixed. Assuming we could fix the temperature as part of the design, we could still only meet one of the two constraints, since the temperatures at which the constraints are met are not equal. ...
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 Spring '08
 MonaHella
 SEPTA Regional Rail, Jaguar Racing, Vin

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