final_sample - Rensselaer Polytechnic Institute ECSE-4220...

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Rensselaer Polytechnic Institute ECSE-4220 VLSI Design Final Sample Questions 1. Analyze the multiple-output dynamic logic circuit shown in Figure 1 and write out the function F1, F2, and F3. A F1= Clk D A C B Clk F2= Clk Clk F3= E Figure 1: . 1
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2. Design a dynamic logic circuit with five inputs: A, B, C, D, and E, and three outputs: F1 =(A+B), F2=(C+D) 0 , and F3=F1 0 F2 0 , using (a) conventional domino logic structure and (b) differential domino logic structure. 2
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3. Given the dynamic circuit as shown in Fig.2. Assume the power supply is 3V. C 1 and C 2 are internal parasitic capacitors and C out is load capacitor. Assume C out = 200 fF and C 1 = C 2 = 20 fF. For the nMOS transistors, we have: V tn 0 = 0 . 5 V, 2 φ F = - 0 . 6 γ = 0 . 4 V 1 / 2 , and the body (i.e., the fourth terminal) of each nMOS transistor is connected to GND. The following table shows the voltages of the input signals during 4 consecutive clock cycles. Fill out the table with the voltages of output signal in the evaluation phase.
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This note was uploaded on 05/04/2009 for the course ECSE 4220 taught by Professor Mcdonald during the Spring '08 term at Rensselaer Polytechnic Institute.

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final_sample - Rensselaer Polytechnic Institute ECSE-4220...

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