final_sample - Rensselaer Polytechnic Institute ECSE-4220...

This preview shows pages 1–4. Sign up to view the full content.

Rensselaer Polytechnic Institute ECSE-4220 VLSI Design Final Sample Questions 1. Analyze the multiple-output dynamic logic circuit shown in Figure 1 and write out the function F1, F2, and F3. A F1= Clk D A C B Clk F2= Clk Clk F3= E Figure 1: . 1

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
2. Design a dynamic logic circuit with ﬁve inputs: A, B, C, D, and E, and three outputs: F1 =(A+B), F2=(C+D) 0 , and F3=F1 0 F2 0 , using (a) conventional domino logic structure and (b) differential domino logic structure. 2
3. Given the dynamic circuit as shown in Fig.2. Assume the power supply is 3V. C 1 and C 2 are internal parasitic capacitors and C out is load capacitor. Assume C out = 200 fF and C 1 = C 2 = 20 fF. For the nMOS transistors, we have: V tn 0 = 0 . 5 V, 2 φ F = - 0 . 6 γ = 0 . 4 V 1 / 2 , and the body (i.e., the fourth terminal) of each nMOS transistor is connected to GND. The following table shows the voltages of the input signals during 4 consecutive clock cycles. Fill out the table with the voltages of output signal in the evaluation phase.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/04/2009 for the course ECSE 4220 taught by Professor Mcdonald during the Spring '08 term at Rensselaer Polytechnic Institute.

Page1 / 6

final_sample - Rensselaer Polytechnic Institute ECSE-4220...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online