# hw2 - OUT is 0.0V at what time will the value of V OUT rise...

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ENGRD2300: Introduction to Digital Logic Fall 2008 Homework 2 Due Wednesday, Sept. 17, at 1:25pm Problem 1. You need to drive a large number of 74HC00-like inputs with 74HC00 NAND gates. What is the maximum number of 74HC00-like inputs that you can connect to one single 74HC00 output without exceeding its worst-case loading specifications (fanout)? Use Wakerly Table 3-3. Hint: Calculate BOTH LOW-state and HIGH-state DC fanouts. Problem 2. Wakerly Drill Problems 3.27 (b), (d), (f) and (g) Problem 3. You are given an inverter driving a 50 pF capacitive load. When the inverter input changes from high to low, the circuit looks as follows: 200 > 1 M 50 pF a) What is the output voltage as a function of time? b) Assuming that at time t = 0, V

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Unformatted text preview: OUT is 0.0V, at what time will the value of V OUT rise to 30% of its final value (i.e., 5.0V)? At what time will the value of V OUT rise to 70% of its final value (i.e., 5.0V)? c) What is t r ? ENGRD2300: Introduction to Digital Logic Fall 2008 Problem 4. Consider the following Boolean expression. F = A •( B + C • D ) + A’• C • D a) Rewrite this expression in sum-of-products form. b) Draw a NAND-NAND logic diagram for the function F. You may use a single NOT gate to produce A’. Problem 5. Recall the Distributivity Theorem (T8’) (X+Y)•(X+Z) = X+(Y•Z) a) Prove this theorem using perfect induction. b) Prove this theorem algebraically. You may use any of the other 1, 2 or 3 variable theorems or axioms....
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hw2 - OUT is 0.0V at what time will the value of V OUT rise...

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