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Unformatted text preview: OUT is 0.0V, at what time will the value of V OUT rise to 30% of its final value (i.e., 5.0V)? At what time will the value of V OUT rise to 70% of its final value (i.e., 5.0V)? c) What is t r ? ENGRD2300: Introduction to Digital Logic Fall 2008 Problem 4. Consider the following Boolean expression. F = A •( B + C • D ) + A’• C • D a) Rewrite this expression in sum-of-products form. b) Draw a NAND-NAND logic diagram for the function F. You may use a single NOT gate to produce A’. Problem 5. Recall the Distributivity Theorem (T8’) (X+Y)•(X+Z) = X+(Y•Z) a) Prove this theorem using perfect induction. b) Prove this theorem algebraically. You may use any of the other 1, 2 or 3 variable theorems or axioms....
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- Fall '07
- 74HC00-like inputs, worst-case loading specifications, inverter input changes, pF capacitive load