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FinalS07sol

# FinalS07sol - ENGRD 230 Introduction to Digital Logic...

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ENGRD 230: Introduction to Digital Logic Design Spring 2007 ENGRD 230 – Spring 2007 Final Exam Wednesday, May 16, 2007 Closed book, closed notes, no calculators Time limit: 150 minutes Academic integrity is expected of all students of Cornell University at all times, whether in the presence or absence of the faculty. Understanding this, I declare I shall not give, use or receive unauthorized aid in this work. ________________________ Signature ________________________ Name ________________________ NetID Please write your NetID at the top of each page of your exam. SHOW ALL OF YOUR WORK!! 1

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ENGRD 230: Introduction to Digital Logic Design Spring 2007 Problem Score 1 /15 2 /24 3 /11 4 /10 5 /15 6 /10 7 /15 Total /100 2
ENGRD 230: Introduction to Digital Logic Design Spring 2007 NET ID: ___________ 1. (15 points) Recall the 8 by 4 SRAM that we covered in class: (a) (5 points) Draw a logic diagram of one of the cells. Recall that both SEL and WR must be asserted for the cell to be written, and the cell is read when SEL is asserted. D Q C IN OUT S EL_L WR_L 3

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ENGRD 230: Introduction to Digital Logic Design Spring 2007 NET ID: ___________ (b) (5 points) Assume that the address lines have been at 000 and both CS_L and OE_L at 0 for a long time. Now WE_L transitions from 1 to 0. Explain what changes occur, if any, to the values in the cells and on the DOUT lines. Cell 0 gets written with the data on the DIN lines and those values also appear on DOUT. (c) (5 points) Modify the partial diagram below to show a design with a bidirectional data bus. That is, the same pins are used for both data inputs and data outputs. 4
ENGRD 230: Introduction to Digital Logic Design Spring 2007 NET ID: ___________ 2. (24 points) Consider the pipelined microprocessor that we covered in class: The machine operates on 8-bit values. That is, the datapaths and values stored in the Register File (RF) and Data RAM (DRAM) are 8 bits wide. (a)

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FinalS07sol - ENGRD 230 Introduction to Digital Logic...

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