FinalS05asol - Practice problems I. PRINT your name:...

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Practice problems I. PRINT your name: Problem 1 [5 points] In Figure 1 a 4-bit parallel register is loaded through a combinational cirtcuit as shown. D 0 D 1 D 3 D 2 REG-4 Q 0 Q 1 Q 3 Q 2 logic 0 X logic 0 logic 0 Figure 1. Assume that the registers at time t = 0 holds some value ( Q 3 Q 2 Q 1 Q 0 ). What is the value the register will hold in time t = 1? ANSWER: ( Q * 3 , Q * 2 , Q * 1 , Q * 0 ) = ( Q 3 , ( Q 2 OR X ) , Q 1 Q 0 )
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PRINT your name: Problem 2 [10 points] You are given 2-input logic gates and the following modules: a 4-bit parallel register (a 4-bit register with parallel load), a 4-bit shift register, mod-4 counter, and 2-to-4 decoder. These are shown in Figure 2. I 0 I 1 I 3 I 2 REG-4 Q 0 Q 1 Q 3 Q 2 Shift_Reg_4 Clock Reset Clock Reset Serial_in Serial_out Count_up Load Clock Carry_out CTR Mod-4 I 0 I 1 Q 0 Q 1 2-to-4 Decoder D 0 D 1 D 3 D 2 A 0 A 1 Enable Shift_Enable (i) Parallel register (ii) Shift register (iii) Counter (iv) Decoder Figure 2. The problem asks you to draw a logic diagram of a system which would transfer the content of the shift register to the parallel register while preserving the original content of the shift register. You can assume that the content of the shift register is given to you, and the initial values stored in the parallel register and the counter are all zeros. The transfer should be accomplished in four clock cycles. You do not have to be concerned with what happens after the transfer is ±nished nor you are required to design a control unit. HINT: Consider using a variant of the circuit shown in Figure 1. REG-4 Shift_Reg_4 Clock Reset Serial_in Serial_out Count_up Load Clock Carry_out CTR Mod-4 I 0 I 1 2-to-4 Decoder D 0 D 1 D 3 D 2 Shift_Enable E I 0 I 1 I 3 I 2 A 0 A 1 Q 0 Q 1 Simpler and more complicated solutions are possible too.
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PRINT your name: Problem 3 [10 points] Draw a logic diagram of a mod-20 counter constructed from external gates and (a) modulo-8 counters, and (b) modulo-4 counters. Block symbols of modulo counters together with a Function Table are shown in Figure 3. (a) modulo-8 counters (b) modulo-4 counters Function Table Count_up Load Clock Carry_out CTR Modulo-8 I 0 I 1 I 2 O 0 O 1 O 2 Count_up Load Clock Carry_out CTR Modulo-4 I 0 I 1 O 0 O 1 Count up Load Action 0 0 no change 0 1 load 1 0 count up 1 1 not de±ned Figure 3. The carry-out from mod-8 counter should be connected to the Count up control of the mod-4 counter. The counters need to be reloaded (with 0) when the joined output becomes 19. (mod-20 counter must go through 20 di²erent states).
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PRINT your name: Problem 4 [10 points] A square array with capacity of 2 20 (1Meg) SR F/Fs forms a basis of a memory module. (By saying a square arry we mean that there is the same number of F/Fs in a column as it is in a row of the array). This module can be con±gured so words of di²erent length can be addressed. A 1D or 2D decoding schemes can be used for addressing words in the module. However, in the 2D decoding scheme the horizontal decoder (the decoder which selects rows in the array) cannot be smaller size than
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This note was uploaded on 05/09/2009 for the course ENGRD 2300 taught by Professor Albonesi/long during the Fall '07 term at Cornell University (Engineering School).

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FinalS05asol - Practice problems I. PRINT your name:...

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