FinalF05 - ENGRD 230: Introduction to Digital Logic Design...

Info iconThis preview shows pages 1–6. Sign up to view the full content.

View Full Document Right Arrow Icon
ENGRD 230: Introduction to Digital Logic Design Fall 2005 1 ENGRD 230 – Fall 2005 Final Exam Tuesday, December 13, 2005 Closed book, closed notes, no calculators Time limit: 150 minutes Academic integrity is expected of all students of Cornell University at all times, whether in the presence or absence of the faculty. Understanding this, I declare I shall not give, use or receive unauthorized aid in this work. ________________________ Signature ________________________ Name ________________________ NetID Please write your NetID at the top of each page of your exam.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ENGRD 230: Introduction to Digital Logic Design Fall 2005 2 Problem Score 1 /10 2 /15 3 /15 4 /15 5 /15 6 /15 7 /15 Total /100
Background image of page 2
ENGRD 230: Introduction to Digital Logic Design Fall 2005 3 Problem 1. (10 points) (a) What is clock skew and why is it a problem? (b) What is the difference between a Mealy and a Moore machine? (c) Define excitation equation, characteristic equation, and transition equation. How are they related?
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ENGRD 230: Introduction to Digital Logic Design Fall 2005 4 Problem 2. (15 points) Construct a Moore type state diagram with one input A and one output Z that has the following behavior. The output is initially 0 The output should change from 0 to 1 or from 1 to 0 whenever the input changes from 0 to 1 The output should not change when the input is a sequence of 1’s The output should not change when the input is a sequence of 0’s The output should not change when the input changes from 1 to 0 For example A: 11111111000000000011111100000000011111111110000000000111111…. Z: 00000000000000000011111111111111100000000000000000000111111…. Draw your state diagram here. Be sure to clearly label your transitions and your outputs.
Background image of page 4
ENGRD 230: Introduction to Digital Logic Design Fall 2005 5 Problem 3. (15 points) A 4-bit dual mode shift register has the following symbol. The function table for this circuit follows:
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 6
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 05/09/2009 for the course ENGRD 2300 taught by Professor Albonesi/long during the Fall '07 term at Cornell University (Engineering School).

Page1 / 11

FinalF05 - ENGRD 230: Introduction to Digital Logic Design...

This preview shows document pages 1 - 6. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online