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Unformatted text preview: b. Simple combination logic has no memory of its past histor; sequential circuits do. c. Never, except for fan-out, but then it is really not combinational. d. Yes. e. The '163 clears only on the rising edge of its clock. The '161 clears as soon as CLR is asserted, independent of its clock. f. Alone as in X&Y it does a bit-by-bit (bitwise) AND. As a pair X&&Y it is used in logical expressions to form a logical AND like in IF statements. Problem 5: a. All CLKs should be tied together. RCO of lsb goes to ENT and ENP of middle counter and to ENP of last counter. RCO of middle counter goes to ENT of last counter. A,B,C,D tied with high or low. CLR, LD, tied high. ENP and ENT of first counter tied high. No Qs should be connected to anything. b. f=16.13 MHz. Last modified on 06/11/18. Direct comments to Wes Swartz ....
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This note was uploaded on 05/09/2009 for the course ENGRD 2300 taught by Professor Albonesi/long during the Fall '07 term at Cornell University (Engineering School).
- Fall '07