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F06prelim2s

# F06prelim2s - b Simple combination logic has no memory of...

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ENGRD 230 Yellow Prelim 2 Answers for Fall 2006 Problem 1: a. State diagram circles from 15 to 0 and back to 15 (a down counter). The output ZERO is high when all 4 outputs are zero. To solve this problem you should have writen the Boolean equations corresponding to the Verilog, and then filled in the transfer truth table. Those that did this scored well; those that didn't didn't. b. See what I said above. Problem 2: a. 0,1,2,4,5,6,7,8,9,0,1,2,... . b. Skip 3 Decade Counter or Divide by 9 counter with skip... . c. 0,1,2,4,5,6,4,5,6,4,5,6,4,... . Problem 3: a. This one takes 3 states. Excitations equations are Q0*=RCO'.Q0 + RCO.Q1' and Q1*=RCo'.Q1.Q0 + RCO.Q1'.Q0 Counter 1: A=0, B=1, C=Q0, D=Q1; Counter 2: A=0, B=1, C=Q1, D=0. Connect LD=RCO' for both counters. Problem 4: a. The output of a D-type latch follows its input so long as it is enabled. A D-type flip-flop transfers the state of the D input to its output on the rising (or falling) edge of its clock.
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Unformatted text preview: b. Simple combination logic has no memory of its past histor; sequential circuits do. c. Never, except for fan-out, but then it is really not combinational. d. Yes. e. The '163 clears only on the rising edge of its clock. The '161 clears as soon as CLR is asserted, independent of its clock. f. Alone as in X&Y it does a bit-by-bit (bitwise) AND. As a pair X&&Y it is used in logical expressions to form a logical AND like in IF statements. Problem 5: a. All CLKs should be tied together. RCO of lsb goes to ENT and ENP of middle counter and to ENP of last counter. RCO of middle counter goes to ENT of last counter. A,B,C,D tied with high or low. CLR, LD, tied high. ENP and ENT of first counter tied high. No Qs should be connected to anything. b. f=16.13 MHz. Last modified on 06/11/18. Direct comments to Wes Swartz ....
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