m2_320w98

# m2_320w98 - 3 R 4 R L v o Circuit for Problem 2 EE 320...

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EE 320 Winter 1998 Prof. Clymer Midterm 2 February 27, 1998 50 minutes Please write out the EE Honor Code Pledge: “No aid given, received or observed,” on this exam booklet and sign your name before turning in your exam.

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EE 320, Midterm 2–Feb. 27, 1998 2 1.) (30 pts) The ideal op amp model uses the two approximations at the input: a.) The voltage diﬀerent between the input terminals (called Δ V in the text and v in in class) is approximately zero, and b.) The current ﬂowing into or out of each input terminal is approximately zero. Noting that this only holds when the op amp operates in a linear fashion, explain in your own words why these two approximations are possible.
EE 320, Midterm 2–Feb. 27, 1998 3 2.) (35 pts) Find the closed loop voltage gain ( A V = v o /v s ) for the circuit shown below. Assume R 1 = 500 Ω, R 2 = 1 KΩ, R 3 = 4 KΩ, R 4 =10KΩand R L = 25 KΩ. Use the ideal model for the op amp. v s + + R 1 R 2 R

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Unformatted text preview: 3 R 4 R L v o Circuit for Problem 2. EE 320, Midterm 2–Feb. 27, 1998 4 3.) (35 pts) Assume that the dc analysis has already performed on the circuit shown below and the dc bias drain current has been determined as I DQ = 0 . 5 mA. The transistor has the following fabrication dependent constants: K = . 0002 A/V 2 , V t = 0 . 7 V, and λ = 0. The resistor values are R 1 = 10 KΩ, R 2 = 2 KΩ and R L = 150 KΩ. The capacitor has an impedance of Z c =-j 1000 Ω. a.) estimate the dc bias value of V GSQ and the small signal parameters g m and r o for the transistor. b.) draw an equivalent small signal ac circuit. (You don’t have to simplify the ac circuit drawing.) c.) ﬁnd the voltage gain, A V = v o /v in . v in ˜ + – R L R 1 v o R 2 C V SS V DD I DQ Circuit for Problem 3. EE 320, Midterm 2–Feb. 27, 1998 5...
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m2_320w98 - 3 R 4 R L v o Circuit for Problem 2 EE 320...

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