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Unformatted text preview: ESE 372/Spring 2009 HW6 .
Due: April 30‘". 4.19. For a particular MOSFET operating in saturation region at a constant VGs, ID is found to be
2mA for VDs=4V and 2.2mA for VDs=8V. What values of to and 7» correspond? 4.58._ An enhancement NMOS transistor is connected in the bias circuit below, with VG=4V and
Rs==le. The transistor has VT=2V and k’n*(W/L)=2mA/V2. What bias current results? If a
transistor for which k’n*(W/L) is 50% higher is used, whatis the resulting percentage increase in
ID? V v 4.59. The bias circuit from 4.58 is used in design with VG=5V and Rs=lk§2. For an enhancement
MOSFET with k’n*(W/L)=2mA/V2, the source voltage (V s) was measured and found to be 2V.
What must be VT be for this device? If a device for which VT is 0.5V less is used, what does Vs
become? What bias current results? 4.60. Design the circuit below for an enhancement MOSFET having VT=2V ' and
k’n*(W/L)=2mAN2. Let VDD=Vss=10V. Design for a dc bias current of lmA and for the largest
possible voltage gain consistent with allowing a 2-V peak-to-peak voltage swing at the drain.
Assume that the signal voltage on the source terminal of the FET is zero. 4.69. Considef the FET ampliﬁer below for the case V1=2V, k’n*(w/L)=1mA/V2, VGS=4V,
VDD=10V, and RD=3.6kQ. , (a) Find the dc ID and VD.
(b) Find g1m at the bias point
(c) Find the value of the voltage gain , Vb” ...
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- Spring '08