ICC compiler implementation user guide.pdf - IC Compiler Implementation User Guide Version J-2014.09-SP2 December 2014 Copyright Notice and Proprietary

ICC compiler implementation user guide.pdf - IC Compiler...

This preview shows page 1 out of 1087 pages.

You've reached the end of your free preview.

Want to read all 1087 pages?

Unformatted text preview: IC Compiler™ Implementation User Guide Version J-2014.09-SP2, December 2014 Copyright Notice and Proprietary Information © 2014 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Trademarks Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at . All other product or company names may be trademarks of their respective owners. Third-Party Links Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not responsible for such websites and their practices, including privacy practices, availability, and content. Synopsys, Inc. 700 E. Middlefield Road Mountain View, CA 94043 IC Compiler™ Implementation User Guide, version J-2014.09-SP2 ii Copyright Notice for the Command-Line Editing Feature © 1992, 1993 The Regents of the University of California. All rights reserved. This code is derived from software contributed to Berkeley by Christos Zoulas of Cornell University. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1.Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2.Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3.All advertising materials mentioning features or use of this software must display the following acknowledgement: This product includes software developed by the University of California, Berkeley and its contributors. 4.Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Copyright Notice for the Line-Editing Library © 1992 Simmule Turner and Rich Salz. All rights reserved. This software is not subject to any license of the American Telephone and Telegraph Company or of the Regents of the University of California. Permission is granted to anyone to use this software for any purpose on any computer system, and to alter it and redistribute it freely, subject to the following restrictions: 1.The authors are not responsible for the consequences of use of this software, no matter how awful, even if they arise from flaws in it. 2.The origin of this software must not be misrepresented, either by explicit claim or by omission. Since few users ever read sources, credits must appear in the documentation. 3.Altered versions must be plainly marked as such, and must not be misrepresented as being the original software. Since few users ever read sources, credits must appear in the documentation. 4.This notice may not be removed or altered. IC Compiler™ Implementation User Guide, version J-2014.09-SP2 iii IC Compiler™ Implementation User Guide, version J-2014.09-SP2 iv Contents About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiv Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxvi Part I: 1. 2. IC Compiler Implementation Flow Introduction to the IC Compiler Tool IC Compiler Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 User Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Methodology Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speeding Up the Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1-7 Working With the IC Compiler Tool Starting the IC Compiler Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Entering icc_shell Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Getting Help on the Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Checking the Syntax and Semantics of Your Scripts . . . . . . . . . . . . . . . . . . . . . . . . Installation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running the Synopsys Syntax Checker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations of the Synopsys Syntax Checker. . . . . . . . . . . . . . . . . . . . . . . . . . . Bytecode-Compiled Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TclPro Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-6 2-7 2-8 2-9 2-9 v IC User Guide Guide IC Compiler™ Compiler™ Implementation Implementation User 3. Version J-2014.09-SP2 J-2014.09-SP2 Working With Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Listing the Licenses in Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Getting Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling License Queuing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Releasing Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2-10 2-10 2-10 2-11 Enabling Multicore Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring Multithreading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring Distributed Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2-12 2-14 Exiting the IC Compiler Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Preparing the Design Setting Up the Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up the Logic Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up the Physical Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Milkyway Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Milkyway Reference Libraries . . . . . . . . . . . . . . . . . . . . . . . Opening a Milkyway Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting a Milkyway Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing Physical Library Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving Physical Library Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verifying the Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-3 3-4 3-5 3-5 3-7 3-7 3-10 3-10 3-11 Reading the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading a Design in Milkyway Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading a Design in .ddc Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading a Design in ASCII Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Incomplete Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-13 3-14 3-15 3-16 Setting the Working Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Current Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opening Designs in a Hierarchical Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traversing Multiple Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing Between Different Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transforming Parent and Child Coordinates . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-17 3-17 3-18 3-19 3-19 Annotating the Floorplan Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading DEF Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading Floorplan Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Copying Floorplan Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3-20 3-21 3-21 Contents vi IC Compiler™ Implementation User Guide Version J-2014.09-SP2 Annotating the Scan Chain Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading a SCANDEF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking Scan Chain Consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Removing SCANDEF Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3-22 3-23 3-23 Specifying the Power Intent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 Validating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Validating the Floorplan Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Validating the Integrity of the Design Database. . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3-25 3-26 Creating Logical Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . Creating the Connections for Single-Voltage Designs . . . . . . . . . . . . . . . . . . . . Creating the Connections for Multivoltage Designs . . . . . . . . . . . . . . . . . . . . . . 3-26 3-27 3-28 Setting Up for Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing Logic Libraries for Leakage-Power Optimization. . . . . . . . . . . . . . . . Identifying Multiple-Threshold-Voltage Cells. . . . . . . . . . . . . . . . . . . . . . . . Analyzing the Multiple-Threshold-Voltage Cell Characteristics . . . . . . . . . Preparing Logic Libraries for Final Stage Leakage-Power Recovery . . . . . Annotating the Switching Activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Multiple-Threshold-Voltage Constraint . . . . . . . . . . . . . . . . . . . . 3-29 3-30 3-30 3-31 3-31 3-32 3-32 Setting Up for Multicorner-Multimode Analysis and Optimization . . . . . . . . . . . . . . . Defining Scenarios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking the Scenario Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Managing the Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Scenarios to Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting the Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Removing Scenarios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3-34 3-35 3-35 3-35 3-38 3-40 Preparing for Timing Analysis and RC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up the TLUPlus Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Operating Condition Analysis Mode . . . . . . . . . . . . . . . . . . . Preparing for Minimum and Maximum Timing Analysis . . . . . . . . . . . . . . . Setting Voltage and Temperature Scaling Between Libraries . . . . . . . . . . . Setting Timing Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting the Delay Calculation Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modifying the RC Coefficients for Preroute RC Estimation . . . . . . . . . . . . . . . . Defining Net-Based Layer Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introducing Pessimism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 3-40 3-42 3-43 3-44 3-46 3-47 3-49 3-50 3-52 3-52 Chapter 1: Contents Contents vii 1-vii IC User Guide Guide IC Compiler™ Compiler™ Implementation Implementation User 4. Version J-2014.09-SP2 J-2014.09-SP2 Back-Annotating Delay or Parasitic Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54 Linking Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linking Designs Without Multicorner-Multimode Scenarios . . . . . . . . . . . . . . . Linking Designs With Multicorner-Multimode Scenarios . . . . . . . . . . . . . . . . . . Resolving References With Operating Condition Mismatches . . . . . . . . . . 3-54 3-55 3-55 3-58 Saving a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving the Design in Milkyway Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving the Design From the Command Line . . . . . . . . . . . . . . . . . . . . . . . Saving the Design in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving the Design Settings in the Milkyway Design Library . . . . . . . . . . . . . . . Saving the Design in ASCII Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing GDSII and OASIS Layout Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60 3-60 3-60 3-61 3-62 3-63 3-64 Closing Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Closing a Milkyway Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66 Archiving Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 Placement and Optimization Preparing for Placement and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Placement Blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Keepout Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Area-Based Placement Blockages . . . . . . . . . . . . . . . . . . . . . . . . Creating Placement Blockages for Thin Channels . . . . . . . . . . . . . . . . . . . Setting the Congestion Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Controlling Placement Density. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Placement Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Move Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Group Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Updating, Querying, and Removing Placement Bounds . . . . . . . . . . . . . . Preventing Cell Placement in the Default Voltage Area . . . . . . . . . . . . . . . . . . . Defining Spacing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Target Library Subsets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining the Buffer Strategy for Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Preferred Buffers for Hold Fixing . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Tie Cell Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preserving dont_touch Nets During Optimization . . . . . . . . . . . . . . . . . . . . . . . Limiting Fanout During Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents 4-2 4-2 4-3 4-5 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-16 4-17 4-18 4-20 4-21 4-21 4-22 4-23 viii IC Compiler™ Implementation User Guide Version J-2014.09-SP2 Setting Placement and Optimization Attributes . . . . . . . . . . . . . . . . . . . . . . . . . Preparing for High-Fanout Net Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Layer Optimization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Layer Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing for Clock Tree Synthesis During Placement . . . . . . . . . . . . . . . . . . . Inserting Port Protection Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up Multithreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4-24 4-24 4-25 4-28 4-29 4-29 Performing Placement and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Placement and Optimization on Designs With Scan Chains. . . . . . Performing Initial Placement on Designs With Scan Chains . . . . . . . . . . . Optimizing the Scan Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up for Dynamic-Power Optimization. . . . . . . . . . . . . . . . . . . . . . . . Setting Up for Leakage-Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . Performing Low-Power Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Leakage-Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Total-Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optimizing Clock-Gating Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reducing the Total Negative Slack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Omitting Initial Placement . . . . ....
View Full Document

  • Fall '18
  • Electronic design automation, Clock distribution network, Tree structure, clock tree, Static timing analysis, Clock Tree Structures

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

Stuck? We have tutors online 24/7 who can help you get unstuck.
A+ icon
Ask Expert Tutors You can ask You can ask You can ask (will expire )
Answers in as fast as 15 minutes