Timing Constraints _ optimization User guide.pdf - Synopsys Timing Constraints and Optimization User Guide Version J-2014.09-SP2 December 2014 Copyright

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Unformatted text preview: Synopsys® Timing Constraints and Optimization User Guide Version J-2014.09-SP2, December 2014 Copyright Notice and Proprietary Information © 2014 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Trademarks Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at . All other product or company names may be trademarks of their respective owners. Third-Party Links Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not responsible for such websites and their practices, including privacy practices, availability, and content. Synopsys, Inc. 700 E. Middlefield Road Mountain View, CA 94043 Synopsys® Timing Constraints and Optimization User Guide, version J-2014.09-SP2 ii Copyright Notice for the Command-Line Editing Feature © 1992, 1993 The Regents of the University of California. All rights reserved. This code is derived from software contributed to Berkeley by Christos Zoulas of Cornell University. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1.Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2.Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3.All advertising materials mentioning features or use of this software must display the following acknowledgement: This product includes software developed by the University of California, Berkeley and its contributors. 4.Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Copyright Notice for the Line-Editing Library © 1992 Simmule Turner and Rich Salz. All rights reserved. This software is not subject to any license of the American Telephone and Telegraph Company or of the Regents of the University of California. Permission is granted to anyone to use this software for any purpose on any computer system, and to alter it and redistribute it freely, subject to the following restrictions: 1.The authors are not responsible for the consequences of use of this software, no matter how awful, even if they arise from flaws in it. 2.The origin of this software must not be misrepresented, either by explicit claim or by omission. Since few users ever read sources, credits must appear in the documentation. 3.Altered versions must be plainly marked as such, and must not be misrepresented as being the original software. Since few users ever read sources, credits must appear in the documentation. 4.This notice may not be removed or altered. Synopsys® Timing Constraints and Optimization User Guide, version J-2014.09-SP2 iii Synopsys® Timing Constraints and Optimization User Guide, version J-2014.09-SP2 iv Contents 1. About This User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvi Customer Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix Introduction to Synthesis Timing Static Timing Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input and Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delay Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip-Flop and Latch Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1-7 1-11 1-12 1-14 1-16 Timing Analysis in the Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synopsys Design Constraint Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Timing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideal Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wire Load Models and Topographical Technology . . . . . . . . . . . . . . . . . . . Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Retiming Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Analysis After Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1-19 1-24 1-26 1-26 1-27 1-29 1-30 1-32 1-34 1-34 1-35 1-36 1-38 1-39 v ® Synopsys Constraints and and Optimization Optimization User User Guide Guide Synopsys® Timing Timing Constraints Version J-2014.09-SP2 J-2014.09-SP2 Synthesis Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. 3. 1-40 Clocks Creating Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Clock Network Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Propagated Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideal Network Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Source Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Uncertainty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideal Clock Transition Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting Clock Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-5 2-5 2-6 2-7 2-8 2-11 2-12 Multiple Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exclusive Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2-14 2-16 2-16 Clock Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Pulse Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Minimum Pulse Width Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 Clock-Gating Signal Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 Generated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Divide-by-2 Generated Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generated Clock Based on Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Divide-by Clock Based on Falling Edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shifting the Edges of a Generated Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combinational-Only Source Latency Calculation . . . . . . . . . . . . . . . . . . . . . . . Generated Clock Based on a Non-Unate Master Clock . . . . . . . . . . . . . . . . . . 2-28 2-29 2-29 2-30 2-32 2-33 2-34 Estimated I/O Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculating I/O Latency for Input Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculating I/O Latency for Output Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 2-38 2-39 Propagated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Timing Paths Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents 3-2 vi Synopsys® Timing Constraints and Optimization User Guide 4. Version J-2014.09-SP2 User Grouping of Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Weight or Cost Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting Path Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2 3-3 3-3 Path Specification Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Through Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rise/Fall From/To Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-5 3-5 Default Path Delay Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Path Delay for Flip-Flops Using a Single Clock . . . . . . . . . . . . . . . . . . . . . . . . . Path Delay for Flip-Flops Using Different Clocks . . . . . . . . . . . . . . . . . . . . . . . . Setup Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hold Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Cycle Path Analysis Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3-8 3-10 3-11 3-11 3-12 Timing Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . False Path Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum and Minimum Path Delay Exceptions . . . . . . . . . . . . . . . . . . . . . . . . Multicycle Path Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Path Timing Margin Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Exceptions Efficiently . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Order of Precedence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Type Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Path Specification Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Removing Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-15 3-16 3-17 3-22 3-23 3-25 3-25 3-25 3-27 3-28 Preset and Clear Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 Data-to-Data Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Data-to-Data Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generating Timing Reports for Data Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Checks and Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library-Based Data Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3-30 3-32 3-32 3-33 Operating Conditions Operating Condition Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Setting Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Operating Condition Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Chapter 1: Contents Contents 1-vii vii ® Synopsys Constraints and and Optimization Optimization User User Guide Guide Synopsys® Timing Timing Constraints Version J-2014.09-SP2 J-2014.09-SP2 Minimum and Maximum Delay Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Min-Max Cell and Net Delay Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setup and Hold Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Path Delay Tracing for Setup and Hold Checks . . . . . . . . . . . . . . . . . . . . . Setup Timing Check for Worst-Case Conditions . . . . . . . . . . . . . . . . . . . . Hold Timing Check for Best-Case Conditions. . . . . . . . . . . . . . . . . . . . . . . Simultaneous Best-Case/Worst-Case Conditions . . . . . . . . . . . . . . . . . . . Path Tracing in On-Chip Variation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-7 4-8 4-8 4-9 4-10 4-11 4-11 Using Two Libraries for Min-Max Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Setting On-Chip Variation Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 Advanced On-Chip Variation Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How AOCV Analysis Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Adjustment Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AOCV Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AOCV Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library-Based AOCV Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File-Based AOCV Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced On-Chip Variation Reporting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Path-Based AOCV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4-15 4-17 4-17 4-17 4-18 4-19 4-21 4-22 Parametric On-Chip Variation Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How POCV Analysis Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parametric On-Chip Variation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POCV Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library-Based POCV Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File-Based POCV Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving Scenario-Specific POCV Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Parametric On-Chip Variation Analysis. . . . . . . . . . . . . . . . . . . . . . . . Reading File-Based Parametric On-Chip Variation Data . . . . . . . . . . . . . . . . . . POCV Guard Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scaling the POCV Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting POCV Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting the POCV Analysis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-31 4-32 4-33 Voltage and Temperature Scaling Between Libraries . . . . . . . . . . . . . . . . . . . . . . . . 4-35 Clock Reconvergence Pessimism Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Variation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reconvergent Logic Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 4-36 4-37 Contents viii Synopsys® Timing Constraints and Optimization User Guide Version J-2014.09-SP2 Setting Clock Reconvergence Pessimism Removal . . . . . . . . . . . . . . . . . . . . . Transparent Latch Edge Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting CRPR Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. 4-38 4-40 4-40 Timing Constraints Input Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Excluding Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-5 5-5 Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Drive Characteristics at Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Port Driving Cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....
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  • Clock signal, Logic gate, Electronic design automation, Flip-flop, timing constraints, Static timing analysis

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