ENGN8537 Lecture 3_ Embedded Processors.pdf

ENGN8537 Lecture 3_ Embedded Processors.pdf - Research...

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Research School of Engineering ENGN8537: Embedded Systems and Real Time Digital Signal Processing You know how aunt Dorothy knew something was going to happen whenever her truss got warm? Well she had nothing on Embedded Processors
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CISC Memory-efficient Complex processor design Slow per-instruction Hard to pipeline Complex Instruction Set Computer vs Reduced Instruction Set Computer. These two terms reflect two different philosophies in the design of a processor’s instruction set and, in turn, the processor architecture. Before the 1970s, all computers were of CISC type. Memory was the supremely limited resource of the time, hardware wasn’t so much of a problem, so the focus was on packing the maximum amount of complexity in to the minimum number of instructions. Memory is now relatively cheap and the focus has moved to performance. This favours the RISC style as simpler instructions are faster to execute
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CISC characterized by Complex Addressing modes Instructions span multiple (and variable) words Specialized instructions implement particular functions Operations can be performed directly on memory locations Memory-to-memory transfers Small program sizes
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RISC Efficient implementations Larger program sizes Efficient to pipeline
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RISC characterized by Simple addressing modes Single word, fixed length instructions Small instruction set of general purpose instructions Operations only performed on registers All memory accesses though a Load/Store architecture Instructions implemented in (the same set of) discrete phases More instructions are required to implement functionality
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Hybrid Designs
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Complex Action RISC instructions becoming more complex. May require hardware accelerators. Since the quantum shift from CISC to RISC styles in the 1970’s, the industry has been slowly incorporating more and more CISC-style functionality in order to reduce the number of instructions executed. This only works if the newly introduced instructions are still fast to execute. A simple example of this is single- instruction floating point operations which, by any definition, are complex operations but may be supported by dedicated FPU hardware to keep the speed up and make them fit the RISC paradigm.
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  • Three '14
  • Central processing unit, Complex instruction set computer

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