Lab 8 Report_ Introduction to Sequential Logic.pdf

Lab 8 Report_ Introduction to Sequential Logic.pdf - Lab 8...

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Lab 8 Report: Introduction to Sequential Logic Name: Meet Patel Section: 511 Date: 5th April, 2018 TA: Zhixing Li
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Objectives: The purpose of lab this week was to introduce sequential logic circuits. To start off, we covered basic storage elements such as latches and flip-flops. We also had the opportunity to describe these components using Verilog in different ways, and then simulate them within Vivado. Next, synchronous sequential circuits were discussed. Furthermore, we added simulation delays into your combinational logic and observe the effects it has on clock timing. Design: This entire lab was constructed within Verilog. We will begin by using structural Verilog to describe different memory components, as well as to simulate them in Xilinx Vivado. Then, we simulated the D-latch using Verilog. With the D-latch module previously created, we constructed a D flip-flop. In Part 2 of the lab, we described the 2-bit synchronous adder and simulated it in Verilog. To understand the effects of combinational circuit delay on a synchronous circuit, we
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  • Spring '08
  • Lu
  • It, Logic gate, 2-bit, nets, time delay, 1-bit, 2bit

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