Exam2_Review.pdf - CMPEN/EE 331 Computer Organization and...

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CMPEN/EE 331 – Computer Organization and Design, Spring 2017 Exam 2 Review Questions 1. Using 32-bit IEEE 754 single precision floating point with one (1) sign bit, eight (8) exponent bits and twenty three (23) mantissa bits, show the representation of -11/16 (-0.6875). 2. What decimal number does the bit pattern 0X0C000000 represent if it is a floating point number? Use the IEEE 754 standard single precision format. 3. Suppose we have just found yet another representation for floating point numbers. Using this representation, a 12-bit floating point number has 1 bit for the sign of the number, 4 bits for the exponent and 7 bits for the mantissa, which is normalized as in the Simple Model so that the first digit to the right of the radix points must be a 1. Numbers in the exponent are in signed 2's complement representation. No bias is used and there are no implied bits. Show the representation for the smallest positive number this machine can represent using the following format (show steps). What decimal number does this equate to? SIGN EXPONENT MANTISSA 4. Compare two pipeline implementations options A and B with 4 and 7 stages, respectively. i. The logic delays of the pipeline stages are follows: Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 6 Stage 7 Option A 250 ps 180 ps 400 ps 200 ps Option B 200 ps 150 ps 250 ps 250 ps 200 ps 150 ps 180 ps What are the maximum clock rates for the two implementations? Option A fs_max = _____ (include the unit with your result) Option B fs_max = _____ (include the unit with your result) ii. The table below states the operation of each pipeline stage: Stage 1 Stage 2 Stage 3 Stage 4 Stage 5 Stage 6 Stage 7 Option A IF/ID EXE MEM WB Option B IF ID EXE-1 EXE-2 EXE-3 MEM WB
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Penn State University School of Electrical Engineering and Computer Science Page 2 of 14 Compared to the MIPS CPU, option A merges IF and ID in a single stage, while option B splits EXE over three pipeline stages. Registers and memory are written to in the first half of the cycle and read during the second half of the cycle (same as MIPS) but there are no forwarding paths. How many instructions are executed after an add and a lw instruction, respectively, before the new register values are available? # nops after add # nops after lw Option A Option B iii. Calculate the number of instructions executed per second for each implementation for the specified fs (these are not necessarily the correct results for part 1) and CPI. f s CPI Instructions per second Option A 3 GHz 1.5 Option B 5 GHz 2.0 5. Consider a processor with the following specification: § Standard five (5) stage (F, D, E, M, W) pipeline. o No forwarding. § Stalls on ALL hazards. § Non-delayed branches § Branch comparison occurs during the second stage. § Instructions are not fetched until branch comparison is done.
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  • Spring '08
  • BHAT
  • Electrical Engineering, Penn State University, School of Electrical Engineering and Computer Science

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