ece314_sec6_TA - ECE/CS 314 Spring 2007 Section 6...

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ECE/CS 314 Spring 2007 - Section 6 - Pipelining Pipelining Performance Definitions: Throughput : The number of instructions completed in a certain length of time Latency : The time taken to complete a given instruction. This is the time taken between fetching an instruction and committing its result at writeback. Pipelining The contents of the data path are broken up into a number of stages. Each pipeline stage takes 1 cycle to perform its action. Thus, the processor clock runs as fast as the slowest pipeline stage. The traditional MIPS pipeline has 5 stages. The standard analogy to think of is an assembly line in a factory. When using pipelines, the throughput of the processor increases, but the latency also can increase. Figure 1: MIPS pipeline diagram
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Pipeline Stages Instruction Fetch (IF) Retrieves instruction words from memory Updates Program Counter (PC) Performs Branch Prediction (you’ll learn more about this later) Instruction Decode (ID) Decode the instruction (split apart the opcode, operands, immediate values) Read the registers used by the instruction Sign extend the offset Execute (EX) Use the ALU for any math or logical instruction Compute the effective address for loads/stores Check branch conditions and compute branch targets (some aggressive implementations do this in the ID stage) Memory Access (M) Read from memory if the instruction was a load Write to memory if the instruction was a store Writeback (WB) If the instruction was a load, write the value returned from memory into the destination register. If the instruction was an ALU instruction, write the result from the calculation into the destination
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This note was uploaded on 03/24/2008 for the course ECE 3140 taught by Professor Mckee/long during the Spring '07 term at Cornell.

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ece314_sec6_TA - ECE/CS 314 Spring 2007 Section 6...

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