L8 Counter.pdf - Topic 8 Counters 1 Counters Count up or...

This preview shows page 1 - 14 out of 43 pages.

1Topic 8Counters
2CountersCount up or count downCount in different format: binary, decimal, one-hot, …Implemented with flip flops – triggered by their clocksCounters:Asynchronous countersSynchronous counters
3Flip flops are not triggered by a global clock signalExample: up counter with T flip flops ClockQ0Q2Q1Count076543218T Q Q Clock T Q Q T Q Q 1 Q 0 Q 1 Q 2 Asynchronous Binary Counter – Ripple Counter
4D Q Q Clock D Q Q DQ Q Q 0 Q 1 Q 2 Example:Alternative binary ripple counter, with D flip flops, up counterAsynchronous Binary Counter – Ripple Counter
5Problem with asynchronous counters:Delays caused by each stage – timing issuesClockQ0Q2Q1Count076543218Asynchronous Binary Counter – Ripple Counter
Synchronous Binary CounterA digital circuit that counts binary numbers – counterAn n-bit binary counter can count in binary from 0 up to 2n-1 and repeat An n-bit binary counter consists of nflip-flopsAll the flip-flops are triggered by (synchronized to) the same clock –synchronous counter May be implemented by different type of flip-flopsExample: a 3-bit binary counter can count through this sequence000001011010111110100101start
Synchronous Binary Counter DesignFollowing the counting sequenceCurrent Value (state)Next Value (state)Q2Q1Q0Q2+Q1+Q0+000001001010010011011100100101101110110111111000
Counter Implemented with D Flip-FlopUse D flip flops to hold valuesQ+= D upon active edgeQ and D are the output and input of a D-FF, respectivelyPresent StateNext StateD flip flop inputQ2Q1Q0Q2+Q1+Q0+D2D1D0000001001001010010010011011011100100100101101101110110110111111111000000
Counter Implemented with D Flip-FlopDrop the columns for Next StatePresent State (D-FF outputs)D flip flop inputsQ2Q1Q0D2D1D0000001001010010011011100100101101110110111111000Truth table inputsTruth table outputsCombinational CircuitQ2Q1Q0D2D1D0
State Registers Implemented with D Flip-Flop000111100001011101Q2D2 = Q2Q1’+Q2Q0’+Q2’Q1Q0= Q2(Q1’+Q0’)+Q2’Q1Q0= Q2(Q1Q0)’+Q2’(Q1Q0)= Q2 (Q1Q0)Q1Q0D2000111100010110101Q2D1 = Q1’Q0+Q1Q0’= Q1 Q0Q1Q0D1000111100100111001Q2D0 = Q0’Q1Q0D0The input equation can be generalized asDn = Qn (Qn-1…Q1Q0)Present StateD flip flop inputQ2Q1Q0D2D1D0000001001010010011011100100101101110110111111000
Synchronous Binary Counter with D Flip-Flop3-bit binary counter by D FF3-bitBinaryCounterQ1Q0clockresetQ2resetDFF2D2Q2Q2clockDFF1D1Q1Q1Q1Q0clearclearDFF0D0Q0Q0clearQ2reset
12Synchronous Binary Counter with D Flip-Flop3-bit binary counter by D FFclockQ1Q0resetQ23-bitBinaryCounterQ1Q0clockresetQ2resetCombinational partSequential part
13Verilog Model: Synchronous Binary Countermodulecounter_N_bit (clock, reset, Q);parameterN = 3;inputclock, reset;output[N-1:0] Q;reg[N-1:0] Q;always@ (posedgereset or posedgeclock) if

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture