lec3-single - EEM 486: Computer Architecture Lecture 3...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
EEM 486: Computer Architecture Lecture 3  Designing a Single Cycle Datapath
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Lec 3.2 The Big Picture: Where are We Now? The Five Classic Components of a Computer Today’s Topic: Design a Single Cycle Processor Control Datapath Memory Processor Input Output
Background image of page 2
Lec 3.3 The Big Picture: The Performance Perspective Performance of a machine is determined by: Instruction count Clock cycle time Clock cycles per instruction Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction CPI Inst. Count Cycle Time
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Lec 3.4 Single-cycle datapath All instructions execute in a single cycle of the       clock  (positive edge to positive edge)   Advantage: a great way to learn CPU   Unrealistic hardware assumptions, slow clock period
Background image of page 4
Lec 3.5  Single cycle data paths: Assumptions Processor uses  synchronous logic design (a “clock”) f T 1 MHz 1 μ s 10 MHz 100 ns 100 MHz 10 ns 1 GHz 1 ns  All state elements act like positive edge- triggered flip flops  Clocks arrive at all flip flops  simultaneously.
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Lec 3.6 Review: Edge-Triggered D Flip Flops D Q Value of D is sampled on  positive clock edge    Q  outputs   sampled   value  for rest of cycle. CLK D Q
Background image of page 6
Lec 3.7 How to Design a Processor: Step-by-Step 1. Analyze instruction set => datapath requirements Meaning of each instruction is given by the  register transfers Datapath must include storage element for ISA registers - possibly more Datapath must support each register transfer 2. Select set of datapath components and establish clocking  methodology 3. Assemble  datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects  the register transfer 5. Assemble the control logic
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Lec 3.8 The MIPS Instruction Formats The three  instruction formats : R-type I-type J-type The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction  op target address 0 26 31 6 bits 26 bits op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt immediate 0 16 21 26 31 6 bits 16 bits 5 bits 5 bits
Background image of page 8
Lec 3.9 Step 1a: The MIPS-lite Subset for Today ADD/SUB addU rd, rs, rt subU rd, rs, rt OR Immediate: ori  rt, rs, imm16 LOAD/STORE Word lw rt, rs, imm16 sw rt, rs, imm16 BRANCH beq rs, rt, imm16 op rs rt rd shamt funct
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/25/2008 for the course ENGINEERIN 486 taught by Professor Atakan during the Spring '08 term at A.T. Still University.

Page1 / 35

lec3-single - EEM 486: Computer Architecture Lecture 3...

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online