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lec3-scontrol - EEM 486 Computer Architecture Lecture 3...

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EEM 486: Computer Architecture Lecture 3 Designing Single Cycle Control
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Lec 3.2 The Big Picture: Where are We Now? Control Datapath Memory Processor Input Output
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Lec 3.3 An Abstract View of the Implementation Data Out Clk 5 Rw Ra Rb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 32 32 32 A B Next Address Control Datapath Control Signals Conditions
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Lec 3.4 Recap: A Single Cycle Datapath We have everything except control signals ( underline ) 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction<31:0> 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt nPC_sel
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Lec 3.5 Recap: Meaning of the Control Signals nPC_MUX_sel:   0   PC <– PC + 4   PC <– PC + 4 + SignExt(Im16) || 00 Adr Inst Memory Adder Adder PC Clk 00 Mux 4 nPC_MUX_sel PC Ext imm16
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Lec 3.6 Recap: Meaning of the Control Signals ExtOp:  “zero”, “sign” ALUsrc:  0   regB; 1   immed ALUctr:  “add”, “sub”, “or” MemWr:  write memory MemtoReg:  ALU; 1   Mem RegDst:  “rt”; 1   “rd” RegWr:  write register 32 ALUctr Clk busW RegWr 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal 0 1 0 1 0 1 =
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Lec 3.7 RTL: The  Add  Instruction add rd, rs, rt mem[PC] Fetch the instruction  from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the next  instruction’s  address op rs rt rd shamt funct 0 6 11 16 21 26 31 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits
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Lec 3.8 Instruction Fetch Unit at the Beginning of  Add Fetch the instruction from Instruction memory:  Instruction  <-  mem[PC]     Same for all instructions    Adr Inst Memory Adder Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction<31:0> 0 1
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Lec 3.9 The Single Cycle Datapath During  Add R[rd]  <-  R[rs]  +  R[rt] 32 ALUctr = Add Clk busW RegWr = 1 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt Rd RegDst = 1 Extender Mux Mux 32 16 imm16 ALUSrc=0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr=0 ALU Instruction Fetch Unit Clk Zero Instruction<31:0> 0 1 0 1 0 1 <21:25> <16:20> <11:15> <0:15> Imm16 Rd Rs Rt nPC_sel= +4
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Lec 3.10 Instruction Fetch Unit at the End of Add PC  <-  PC + 4 This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction<31:0> 0 1
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Lec 3.11 The Single Cycle Datapath During Or Immediate R[rt]  <-  R[rs]  or  ZeroExt[Imm16] RegDst = 32 ALUctr = Clk busW RegWr = 32 32 busA 32 busB 5 5 5 Rw Ra Rb 32 32-bit Registers Rs Rt Rt
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