qsys_interconnect.pdf - Qsys Interconnect 7 2014.08.18 QII51021 Subscribe Send Feedback Qsys interconnect is a high-bandwidth structure for connecting

qsys_interconnect.pdf - Qsys Interconnect 7 2014.08.18...

This preview shows page 1 out of 65 pages.

You've reached the end of your free preview.

Want to read all 65 pages?

Unformatted text preview: Qsys Interconnect 7 2014.08.18 QII51021 Subscribe Send Feedback Qsys interconnect is a high-bandwidth structure for connecting components, and that allows you to connect ® ® ™ IP cores to other IP cores with various interfaces. Qsys supports standard Avalon , AMBA AXI3 (version ™ ™ 1.0), AMBA AXI4 (version 2.0), AMBA AXI4-Lite (version 2.0), AMBA AXI4-Stream (version 1.0), and ™ AMBA APB 3 (version 1.0) interfaces. Related Information • Avalon Interface Specifications • AMBA Specifications • Creating a System with Qsys • Creating Qsys Components • Qsys System Design Components Memory-Mapped Interfaces Qsys supports the implementation of memory-mapped interfaces for Avalon, AXI, and APB protocols. Qsys interconnect transmits memory-mapped transactions between masters and slaves in packets. The command network transports read and write packets from master interfaces to slave interfaces. The response network transports response packets from slave interfaces to master interfaces. For each component interface, Qsys interconnect manages memory-mapped transfers and interacts with signals on the connected interface. Master and slave interfaces can implement different signals based on interface parameterizations, and Qsys interconnect provides any necessary adaptation between them. In the path between master and slaves, Qsys interconnect may introduce registers for timing synchronization, finite state machines for event sequencing, or nothing at all, depending on the services required by the interfaces. Qsys interconnect supports the following implementation scenarios: • Any number of components with master and slave interfaces. The master-to-slave relationship can be one-to-one, one-to-many, many-to-one, or many-to-many. • Masters and slaves of different data widths. • Masters and slaves operating in different clock domains. © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at . Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 7-2 Memory-Mapped Interfaces QII51021 2014.08.18 • IP Components with different interface properties and signals. Qsys adapts the component interfaces so that interfaces with the following differences can be connected: • Avalon and AXI interfaces that use active-high and active-low signaling. AXI signals are active high, except for the reset signal. • Interfaces with different burst characteristics. • Interfaces with different latencies. • Interfaces with different data widths. • Interfaces with different optional interface signals. Note: AXI3/4 to AXI3/4 interface connections declare a fixed set of signals with variable latency. As a result, there is no need for adapting between active-low and active-high signaling, burst characteristics, different latencies, or port signatures. Some adaptation may be necessary between Avalon interfaces. Altera Corporation Qsys Interconnect Send Feedback QII51021 2014.08.18 Packet Format for Memory-Mapped Interfaces 7-3 Figure 7-1: Qsys interconnect for an Avalon-MM System with Multiple Masters In this example, there are two components mastering the system, a processor and a DMA controller, each with two master interfaces. The masters connect through the Qsys interconnect to several slaves in the Qsys system. The blue blocks represent interconnect components. The dark grey boxes indicate items outside of the Qsys system and the Quartus II software design, and show how component interfaces can be exported and connected to external devices. PCB Instruction M Master Network Interface S Control Qsys Design in Altera FPGA Processor DMA Controller Data M Master Network Interface Interconnect Read M Write M Master Network Interface Master Network Interface Command Switch (Avalon-ST) Slave Network Interface S Instruction Memory Response Switch (Avalon-ST) Slave Network Interface Slave Network Interface Slave Network Interface S S S S Data Memory DDR3 Controller Tri-State Controller Tri-State Conduit TCM TCM TCS TCS Master Command Connectivity Slave Response Connectivity Interface to Off-Chip Device M Avalon-MM Master Interface S Avalon-MM Slave Interface TCM Avalon Tri-State Conduit Master Tri-State Conduit Pin Sharer & Bridge DDR3 Chip TCS Avalon Tri-State Conduit Slave S S Ethernet MAC/PHY Chip Flash Memory Chip Packet Format for Memory-Mapped Interfaces The Qsys packet format supports Avalon, AXI, and APB transactions. Memory-mapped transactions between masters and slaves are encapsulated in Qsys packets. For Avalon systems without AXI or APB interfaces, some fields are ignored or removed. Qsys Interconnect Send Feedback Altera Corporation 7-4 QII51021 2014.08.18 Qsys Packet Format Qsys Packet Format Table 7-1: Qsys Packet Format for Memory-Mapped Master and Slave Interfaces The fields of the Qsys packet format are of variable length to minimize resource usage. However, if the majority of components in a design have a single data width, for example 32-bits, and a single component has a data width of 64-bits, Qsys inserts a width adapter to accommodate 64-bit transfers. Command Description Address Specifies the byte address for the lowest byte in the current cycle. There are no restrictions on address alignment. Size Encodes the run-time size of the transaction. In conjunction with address, this field describes the segment of the payload that contains valid data for a beat within the packet. Address Sideband Carries “address” sideband signals. The interconnect passes this field from master to slave. This field is valid for each beat in a packet, even though it is only produced and consumed by an address cycle. Up to 8-bit sideband signals are supported for both read and write address channels. Cache Carries the AXI cache signals. Transaction (Exclusive) Indicates whether the transaction has exclusive access. Transaction (Posted) Used to indicate non-posted writes (writes that require responses). Data For command packets, carries the data to be written. For read response packets, carries the data that has been read. Byteenable Specifies which symbols are valid. AXI can issue or accept any byteenable pattern. For compatibility with Avalon, Altera recommends that you use the following legal values for 32-bit data transactions between Avalon masters and slaves: • • • • • • • 1111—Writes full 32 bits 0011—Writes lower 2 bytes 1100—Writes upper 2 bytes 0001—Writes byte 0 only 0010—Writes byte 1 only 0100—Writes byte 2 only 1000—Writes byte 3 only Source_ID The ID of the master or slave that initiated the command or response. Destination_ID The ID of the master or slave to which the command or response is directed. Response Carries the AXI response signals. Thread ID Carries the AXI transaction ID values. Altera Corporation Qsys Interconnect Send Feedback QII51021 2014.08.18 Qsys Packet Format Command 7-5 Description Byte count The number of bytes remaining in the transaction, including this beat. Number of bytes requested by the packet. Burstwrap The burstwrap value specifies the wrapping behavior of the current burst. The burstwrap value is of the form 2<n> -1. The following types are defined: • Variable wrap–Variable wrap bursts can wrap at any integer power of 2 value. When the burst reaches the wrap boundary, it wraps back to the previous burst boundary so that only the low order bits are used for addressing. For example, a burst starting at address 0x1C, with a burst wrap boundary of 32 bytes and a burst size of 20 bytes, would write to addresses 0x1C, 0x0, 0x4, 0x8, and 0xC. • For a burst wrap boundary of size <m>, Burstwrap = <m> - 1, or for this case 5 Burstwrap = (32 - 1) = 31 which is 2 -1. • For AXI masters, the burstwrap boundary value (m) is based on the different AXBURST: • Burstwrap set to all 1’s. For example, for a 6-bit burstwrap, burstwrap is 6'b111111. • For WRAP bursts, burstwrap = AXLEN * size – 1 • For FIXED bursts, burstwrap = size – 1 • Sequential–Sequential bursts increment the address for each transfer in the burst. For sequential bursts, the Burstwrap field is set to all 1s. For example, with a 6-bit Burstwrap field, the value for a sequential burst is 6'b111111 or 63, which is 26 - 1. For Avalon masters, Qsys adaptation logic sets a hardwired value for the burstwrap field, according the declared master burst properties. For example, for a master that declares sequential bursting, the burstwrap field is set to ones. Similarly, masters that declare burst have their burstwrap field set to the appropriate constant value. AXI masters choose their burst type at run-time, depending on the value of the AW or ARBURST signal. The interconnect calculates the burstwrap value at run-time for AXI masters. Protection Access level protection. When the lowest bit is 0, the packet has normal access. When the lowest bit is 1, the packet has privileged access. For Avalon-MM interfaces, this field maps directly to the privileged access signal, which allows an memory-mapped master to write to an on-chip memory ROM instance. The other bits in this field support AXI secure accesses and uses the same encoding, as described in the AXI specification. QoS QoS (Quality of Service Signaling) is a 4-bit field that is part of the AXI4 interface that carries QoS information for the packet from the AXI master to the AXI slave. Transactions from AXI3 and Avalon masters have the default value 4'b0000, that indicates that they are not participating in the QoS scheme. QoS values are dropped for slaves that do not support QoS. Qsys Interconnect Send Feedback Altera Corporation 7-6 QII51021 2014.08.18 Transaction Types for Memory-Mapped Interfaces Command Description Carries data sideband signals for the packet. On a write command, the data sideband directly maps to WUSER. On a read response, the data sideband directly maps to RUSER. On a write response, the data sideband directly maps to BUSER. Data sideband Transaction Types for Memory-Mapped Interfaces Table 7-2: Transaction Types for Memory-Mapped Interfaces The table below describes the information that each bit transports in the packet format's transaction field. Bit Name Definition 0 PKT_TRANS_READ When asserted, indicates a read transaction. 1 PKT_TRANS_COMPRESSED_READ For read transactions, specifies whether or not the read command can be expressed in a single cycle, that is whether or not it has all byteenables asserted on every cycle. 2 PKT_TRANS_WRITE When asserted, indicates a write transaction. 3 PKT_TRANS_POSTED When asserted, no response is required. 4 PKT_TRANS_LOCK When asserted, indicates arbitration is locked. Applies to write packets. Interconnect Domains An interconnect domain is a group of connected memory-mapped masters and slaves that share the same interconnect. The components in a single interconnect domain share the same packet format. Using One Domain with Width Adaptation When one of the masters in a system connects to all of the slaves, Qsys creates a single domain with two packet formats: one with 64-bit data, and one with 16-bit data. A width adapter manages accesses between the 16-bit master and 64-bit slaves. Altera Corporation Qsys Interconnect Send Feedback QII51021 2014.08.18 Using One Domain with Width Adaptation 7-7 Figure 7-2: One Domain with 1:4 and 4:1 Width Adapters In this system example, there are two 64-bit masters that access two 64-bit slaves. It also includes one 16-bit master, that accesses two 16-bit slaves and two 64-bit slaves. The 16-bit Avalon master connects through a 1:4 adapter, then a 4:1 adapter to reach its 16-bit slaves. Single Domain with 1:4 & 4:1 Width Adapters 64-Bit Avalon-MM Master M 1:4 S 64-Bit Avalon-MM Slave Qsys Interconnect Send Feedback 64-Bit Avalon-MM Master M 4:1 16-Bit Avalon-MM Master M S S 16-Bit Avalon-MM Slave 16-Bit Avalon-MM Slave S 64-Bit Avalon-MM Slave Altera Corporation 7-8 QII51021 2014.08.18 Using Two Separate Domains Using Two Separate Domains Figure 7-3: Two Separate Domains In this system example, Qsys uses two separate domains. The first domain includes two 64-bit masters connected to two 64-bit slaves. A second domain includes one 16-bit master connected to two 16-bit slaves. Because the interfaces in Domain 1 and Domain 2 do not share any connections, Qsys can optimize the packet format for the two separate domains. In this example, the first domain uses a 64-bit data width and the second domain uses 16-bit data. Component 2 Component 1 64-bit Avalon-MM Master 64-bit Avalon-MM Master 16-bit Avalon-MM Master M M M Domain 1 Domain 2 S S S S 64-bit Avalon-MM Slave 64-bit Avalon-MM Slave 16-bit Avalon-MM Slave 16-bit Avalon-MM Slave Command Network Response Network Qsys Transformations The memory-mapped master and slave components connect to network interface modules that encapsulate the transaction in Avalon-ST packets. The memory-mapped interfaces have no information about the encapsulation or the function of the layer transporting the packets. The interfaces simply operate in accordance with memory-mapped protocol ans use the read and write signals and transfers as defined in the Avalon or AXI specifications. Altera Corporation Qsys Interconnect Send Feedback QII51021 2014.08.18 Master Network Interfaces 7-9 Figure 7-4: Transformation when Generating a System with Memory-Mapped and Slave Components In this system example, the Qsys components that implement the blocks appear shaded. Avalon-MM or AXI Avalon-ST Master Interface Master Network Interface Master Interface Master Network Interface Avalon-MM or AXI Avalon-ST Network (Command) Avalon-ST Network (Response) Slave Network Interface Slave Interface Slave Network Interface Slave Interface Master Command Connectivity Slave Response Connectivity Related Information • Master Network Interfaces on page 7-9 • Slave Network Interfaces on page 7-12 Master Network Interfaces Figure 7-5: Avalon-MM Master Network Interface Avalon network interfaces drive default values for the QoS and BUSER, WUSER, and RUSER packet fields in the master agent, and drop the packet fields in the slave agent. Master Network Interface Avalon-ST Network (Command) Router Master Interface Translator Agent Limiter Avalon-ST Network (Response) Qsys Interconnect Send Feedback Altera Corporation 7-10 QII51021 2014.08.18 Avalon-MM Master Agent Figure 7-6: AXI Master Network Interface An AXI4 master supports INCR bursts up to 256 beats, QoS signals, and data sideband signals. Master Network Interface Read Command Master Interface AXI Translator AXI Master Agent Write Command Router Router Limiter Avalon-ST Network (Command) Write Response Read Response Limiter Avalon-ST Network (Response) Avalon-MM Master Agent The Avalon-MM Master Agent translates Avalon-MM master transactions into Qsys command packets and translates the Qsys Avalon-MM slave response packets into Avalon-MM responses. Avalon-MM Master Translator The Avalon-MM Master Translator interfaces with an Avalon-MM master component and converts the Avalon-MM master interface to a simpler representation for use in Qsys. The Avalon-MM Master translator performs the following functions: • • • • • • Translates active-low signaling to active-high signaling Inserts wait states to prevent an Avalon-MM master from reading invalid data Translates word and symbol addresses Translates word and symbol burst counts Manages re-timing and re-sequencing bursts Removes unnecessary address bits AXI Master Agent An AXI Master Agent accepts AXI commands and produces Qsys command packets. It also accepts Qsys response packets and converts those into AXI responses. This component has separate packet channels for read commands, write commands, read responses, and write responses. Avalon master agent drives the QoS and BUSER, WUSER, and RUSER packet fields with default values AXQO and b0000, respectively. Note: For signal descriptions, refer to Qsys Packet Format. Related Information Qsys Packet Format on page 7-4 AXI Translator AXI4 allows some signals to be omitted from interfaces. The translator bridges between these “incomplete” AXI4 interfaces and the “complete” AXI4 interface on the network interfaces. Altera Corporation Qsys Interconnect Send Feedback QII51021 2014.08.18 APB Master Agent 7-11 The AXI translator is inserted for both AXI4 masters and slaves and performs the following functions: • Matches ID widths between the master and slave in 1x1 systems. • Drives default values as defined in the AMBA Protocol Specifications for missing signals. • Performs lock transaction bit conversion when an AXI3 master connects to an AXI4 slave in 1x1 systems. Related Information AMBA Protocol Specifications APB Master Agent An APB master agent accepts APB commands and produces or generates Qsys command packets. It also converts Qsys response packets to APB responses. APB Slave Agent An APB slave agent issues resulting transaction to the APB interface. It also accepts creates Qsys response packets. APB Translator An APB peripheral does not require pslverr signals to support additional signals for the APB debug interface. The APB translator is inserted for both the master and slave and performs the following functions: • Sets the response value default to OKAY if the APB slave does not have a pslverr signal. • Turns on or off additional signals between the APB debug interface, which is used with HPS (Altera SoC’s Hard Processor System). Memory-Mapped Router The Memory-Mapped Router routes command packets from the master to the slave, and response packets from the slave to the master. For master command packets, the router uses the address to set the Destination_ID and Avalon-ST channel. For the slave response packet, the router uses the Destination_ID to set the Avalon-ST channel. The demultiplexers use the Avalon-ST channel to route the packet to the correct destination. Memory-Mapped Traffic Limiter The Memory-Mapped Traffic Limiter ensures the responses arrive in order. It prevents any command from being sent if the response could conflict with the response for a command that has already been issued. By guaranteeing in-order responses, the Traffic Limiter simplifies the response network. Qsys Interconnect Send Feedback Altera Corporation 7-12 QII51021 2014.08.18 Slave Network Interfaces Slave Network Interfaces Figure 7-7: Avalon-MM Slave Network Interface Slave Network Interface Avalon-ST Network (Command) Overflow Error Command Waitrequest Agent Avalon-ST Network (Response) Translator Slave Interface Response Figure 7-8: AXI Slave Network Interface An AXI4 slave supports up to 256 beat INCR bursts, QoS signals, and data sideband signals. Network Interface Avalon-ST Network (Command) Write Command Read Command AXI Agent Avalon-ST Network (Response) AXI Translator Slave Interface Write Response Read Response Avalon-MM Slave Translator The Avalon-MM Slave Translator interfaces to an Avalon-MM slave component as the Avalon-MM Slave Network Interface figure illustrates. It converts the Avalon-MM slave interface to a simplified representation that the Qsys network can use. An Avalon-MM Merlin Slave Translator performs the following functions: • Drives the begintransfer,...
View Full Document

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture