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Unformatted text preview: SystemVerilog
For Design
Second Edition
A Guide to Using SystemVerilog
for Hardware Design and Modeling SystemVerilog
For Design
Second Edition
A Guide to Using SystemVerilog
for Hardware Design and Modeling
by
Stuart Sutherland
Simon Davidmann
Peter Flake
Foreword by Phil Moorby 13 Stuart Sutherland
Sutherland DHL, Inc.
22805 SW 92nd Place
Tualatin, OR 97062
USA
Simon Davidmann
The Old Vicerage
Priest End
Thame, Oxfordshire 0X9 3AB
United Kingdom
Peter Flake
Imperas, Ltd.
Imperas Buildings, North Weston
Thame, Oxfordshire 0X9 2HA
United Kingdom SystemVerilog for Design, Second Edition
A Guide to Using SystemVerilog for Hardware Design and Modeling Library of Congress Control Number:
ISBN-10: 0-387-33399-1
ISBN-13: 9780387333991 2006928944
e-ISBN-10: 0-387-36495-1
e-ISBN-13: 9780387364957 Printed on acid-free paper.
© 2006 Springer Science+Business Media, LLC
All rights reserved. This work may not be translated or copied in whole or in part without
the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring
Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or
scholarly analysis. Use in connection with any form of information storage and retrieval,
electronic adaptation, computer software, or by similar or dissimilar methodology now
known or hereafter developed is forbidden.
The use in this publication of trade names, trademarks, service marks and similar terms,
even if they are not identified as such, is not to be taken as an expression of opinion as to
whether or not they are subject to proprietary rights.
Printed in the United States of America.
9 8 7 6 5 4 3 2
springer.com Dedications To my wonderful wife, LeeAnn, and my children, Ammon, Tamara, Hannah, Seth and
Samuel — thank you for all your patience during the many long hours and late nights
while writing this book.
Stuart Sutherland
Portland, Oregon To all of the staff of Co-Design and the many EDA colleagues that worked with me
over the years — thank you for helping to evolve Verilog and make its extension and
evolution a reality. And to Penny, Emma and Charles — thank you for allowing me
the time to indulge in language design (and in cars and guitars...).
Simon Davidmann
Santa Clara, California To my wife Monique, for supporting me when I was not working, and when I was
working too much.
Peter Flake
Thame, UK Table of Contents Foreword ................................................................................................................. xxi
Preface ................................................................................................................... xxiii
Target audience...................................................................................................................... xxiii
Topics covered........................................................................................................................xxiv
About the examples in this book..............................................................................................xxv
Obtaining copies of the examples...........................................................................................xxvi
Example testing.......................................................................................................................xxvi
Other sources of information .................................................................................................xxvii
Acknowledgements..................................................................................................................xxx Chapter 1: Introduction to SystemVerilog...............................................................1
1.1 1.2
1.3 SystemVerilog origins.......................................................................................................1
1.1.1 Generations of the SystemVerilog standard.......................................................2
1.1.2 Donations to SystemVerilog ..............................................................................4
Key SystemVerilog enhancements for hardware design...................................................5
Summary ...........................................................................................................................6 Chapter 2: SystemVerilog Declaration Spaces ........................................................7
2.1 2.2 2.3
2.4 Packages ...........................................................................................................................8
2.1.1 Package definitions ............................................................................................9
2.1.2 Referencing package contents..........................................................................10
2.1.3 Synthesis guidelines .........................................................................................14
$unit compilation-unit declarations.................................................................................14
2.2.1 Coding guidelines.............................................................................................17
2.2.2 SystemVerilog identifier search rules ..............................................................17
2.2.3 Source code order.............................................................................................17
2.2.4 Coding guidelines for importing packages into $unit ......................................19
2.2.5 Synthesis guidelines .........................................................................................25
Declarations in unnamed statement blocks .....................................................................26
2.3.1 Local variables in unnamed blocks ..................................................................27
Simulation time units and precision ................................................................................28
2.4.1 Verilog’s timescale directive............................................................................28
2.4.2 Time values with time units .............................................................................30
2.4.3 Scope-level time unit and precision .................................................................31 2.5 2.4.4 Compilation-unit time units and precision.......................................................32
Summary .........................................................................................................................34 Chapter 3: SystemVerilog Literal Values and Built-in Data Types.....................37
3.1
3.2 Enhanced literal value assignments.................................................................................38
‘define enhancements ......................................................................................................39
3.2.1 Macro argument substitution within strings.....................................................39
3.2.2 Constructing identifier names from macros .....................................................41
3.3 SystemVerilog variables..................................................................................................42
3.3.1 Object types and data types..............................................................................42
3.3.2 SystemVerilog 4-state variables.......................................................................43
3.3.3 SystemVerilog 2-state variables.......................................................................44
3.3.4 Explicit and implicit variable and net data types .............................................47
3.3.5 Synthesis guidelines .........................................................................................48
3.4 Using 2-state types in RTL models .................................................................................48
3.4.1 2-state type characteristics ...............................................................................49
3.4.2 2-state types versus 2-state simulation .............................................................49
3.4.3 Using 2-state types with case statements .........................................................51
3.5 Relaxation of type rules...................................................................................................52
3.6 Signed and unsigned modifiers .......................................................................................55
3.7 Static and automatic variables .........................................................................................56
3.7.1 Static and automatic variable initialization ......................................................59
3.7.2 Synthesis guidelines for automatic variables ...................................................60
3.7.3 Guidelines for using static and automatic variables.........................................61
3.8 Deterministic variable initialization ................................................................................61
3.8.1 Initialization determinism ................................................................................61
3.8.2 Initializing sequential logic asynchronous inputs ............................................65
3.9 Type casting ....................................................................................................................67
3.9.1 Static (compile time) casting............................................................................67
3.9.2 Dynamic casting...............................................................................................69
3.9.3 Synthesis guidelines .........................................................................................70
3.10 Constants .........................................................................................................................71
3.11 Summary .........................................................................................................................72 Chapter 4: SystemVerilog User-Defined and Enumerated Types .......................75
4.1 4.2 User-defined types...........................................................................................................75
4.1.1 Local typedef definitions..................................................................................76
4.1.2 Shared typedef definitions................................................................................76
4.1.3 Naming convention for user-defined types ......................................................78
Enumerated types ............................................................................................................79
4.2.1 Enumerated type label sequences.....................................................................83 viii 4.3 4.2.2 Enumerated type label scope............................................................................83
4.2.3 Enumerated type values ...................................................................................84
4.2.4 Base type of enumerated types.........................................................................85
4.2.5 Typed and anonymous enumerations...............................................................86
4.2.6 Strong typing on enumerated type operations..................................................86
4.2.7 Casting expressions to enumerated types.........................................................88
4.2.8 Special system tasks and methods for enumerated types.................................89
4.2.9 Printing enumerated types................................................................................92
Summary .........................................................................................................................93 Chapter 5: SystemVerilog Arrays, Structures and Unions ..................................95
5.1 5.2 5.3 5.4 Structures.........................................................................................................................96
5.1.1 Structure declarations.......................................................................................97
5.1.2 Assigning values to structures..........................................................................98
5.1.3 Packed and unpacked structures.....................................................................101
5.1.4 Passing structures through ports.....................................................................104
5.1.5 Passing structures as arguments to tasks and functions .................................105
5.1.6 Synthesis guidelines .......................................................................................105
Unions ...........................................................................................................................105
5.2.1 Unpacked unions ............................................................................................106
5.2.2 Tagged unions ................................................................................................108
5.2.3 Packed unions.................................................................................................109
5.2.4 Synthesis guidelines .......................................................................................111
5.2.5 An example of using structures and unions ...................................................111
Arrays ............................................................................................................................113
5.3.1 Unpacked arrays.............................................................................................113
5.3.2 Packed arrays .................................................................................................116
5.3.3 Using packed and unpacked arrays ................................................................118
5.3.4 Initializing arrays at declaration.....................................................................119
5.3.5 Assigning values to arrays .............................................................................121
5.3.6 Copying arrays ...............................................................................................123
5.3.7 Copying arrays and structures using bit-stream casting.................................124
5.3.8 Arrays of arrays..............................................................................................125
5.3.9 Using user-defined types with arrays .............................................................126
5.3.10 Passing arrays through ports and to tasks and functions................................127
5.3.11 Arrays of structures and unions......................................................................128
5.3.12 Arrays in structures and unions......................................................................128
5.3.13 Synthesis guidelines .......................................................................................128
5.3.14 An example of using arrays............................................................................129
The foreach array looping construct..............................................................................130 ix 5.5
5.6
5.7
5.8 Array querying system functions ..................................................................................132
The $bits “sizeof” system function ...............................................................................134
Dynamic arrays, associative arrays, sparse arrays and strings ......................................135
Summary .......................................................................................................................136 Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions ................137
6.1
6.2 6.3 6.4 Verilog general purpose always procedural block ........................................................138
SystemVerilog specialized procedural blocks...............................................................142
6.2.1 Combinational logic procedural blocks .........................................................142
6.2.2 Latched logic procedural blocks ....................................................................150
6.2.3 Sequential logic procedural blocks ................................................................152
6.2.4 Synthesis guidelines .......................................................................................152
Enhancements to tasks and functions ............................................................................153
6.3.1 Implicit task and function statement grouping...............................................153
6.3.2 Returning function values ..............................................................................153
6.3.3 Returning before the end of tasks and functions ............................................154
6.3.4 Void functions ................................................................................................155
6.3.5 Passing task/function arguments by name .....................................................156
6.3.6 Enhanced function formal arguments ............................................................157
6.3.7 Functions with no formal arguments..............................................................158
6.3.8 Default formal argument direction and type ..................................................158
6.3.9 Default formal argument values.....................................................................159
6.3.10 Arrays, structures and unions as formal arguments .......................................160
6.3.11 Passing argument values by reference instead of copy ..................................161
6.3.12 Named task and function ends .......................................................................165
6.3.13 Empty tasks and functions .............................................................................166
Summary .......................................................................................................................166 Chapter 7: SystemVerilog Procedural Statements..............................................169
7.1 7.2 7.3 New operators................................................................................................................170
7.1.1 Increment and decrement operators ...............................................................170
7.1.2 Assignment operators.....................................................................................173
7.1.3 Equality operators with don’t care wildcards.................................................176
7.1.4 Set membership operator — inside ................................................................178
Operand enhancements..................................................................................................180
7.2.1 Operations on 2-state and 4-state types..........................................................180
7.2.2 Type casting ...................................................................................................180
7.2.3 Size casting.....................................................................................................181
7.2.4 Sign casting ....................................................................................................182
Enhanced for loops ........................................................................................................182
7.3.1 Local variables within for loop declarations ..................................................183 x 7.3.2 Multiple for loop assignments........................................................................185
7.3.3 Hierarchically referencing variables declared in for loops ............................185
7.3.4 Synthesis guidelines .......................................................................................186
7.4 Bottom testing do...while loop ................................
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