HW6_Solution.pdf - CPRE 381 HW 6 solution Due 10/26 9:00am...

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Chapter 11 / Exercise 11.23
Digital Systems Design Using VHDL
John/Roth
Expert Verified
1 CPRE 381: HW 6 solution Due: 10/26, 9:00am Max points: 100 (+ bonus points) 1) Single-Cycle MIPS Enhancements (pts: 35) # max max Solution [a] 10 5 Q) Add jr (jump register) to the diagram (Fig. 4.21) 1) Add a 32-bit 2:1 mux (called JR mux) after the Branch decision mux and before the PC register. 2) Introduce a new control signal to the Control component as an output, label it as ‘JR’ and link the signal to the JR decision mux as a selection signal. 3) The two inputs to the JR decision mux are: For JR = 0 : the output of the Branch decision mux For JR = 1 : the output of the Read data 1 from the RegFile 5 Q) Add jr (jump register) to the table (Fig. 4.22) Have the funct code be the second input to the Control component so that it can differentiate jr (R-type) from the rest R-type instructions. In/out Sig. name R-format Lw Sw beq Non-jr jr In Op 5 0 Op 4 0 Op 3 0 Op 2 0 Op 1 0 Op 0 0 Funct 5 anything except 08 hex 0 Don’t care (X) Funct 4 0 Funct 3 1 Funct 2 0 Funct 1 0 Funct 0 0 Out RegDst X ALUSrc X MemtoReg X RegWrite 0 MemRead 0 MemWrite 0 Branch 0 ALUOp1 X ALUOp0 X JR 0 1 0 0 0 The don’t care bit ‘X’ can be set to ‘0’, ‘1’ or ‘X’ since we really don’t care.
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Chapter 11 / Exercise 11.23
Digital Systems Design Using VHDL
John/Roth
Expert Verified
2 [b] 10 5 Q) Add lui (load upper imme) to the diagram (Fig. 4.21) Two options. [Option 1] For lui, let ALUSrc mux to pass the sign-extended imme value and then let ALU perform SLL <<16 on the 2 nd 1) Introduce a new 32-bit 2:1 mux (called lui mux) after the MemtoReg mux. input. [Option 2] 2) Introduce a new control signal to the Control component as an output, label it as lui, and link it to the lui mux. 3) Prepare the lui result: e.g., perform SLL<<16 on the output of the 16:32 sign-extender or perform Instruction[15..0] & 0000 4) Map the input of the lui decision mux as: hex a. For lui = 0