Computer Science 152 - Fall 2000 - Brodersen - Midterm 1

# Computer Science 152 - Fall 2000 - Brodersen - Midterm 1 -...

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University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Science CS152 Midterm Solution Prof. Bob Brodersen Fall, 2000

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Problem 1: Single-cycle Processor and Performance Evaluation We have a single cycle processor as we learned in class. Besides the instructions R-format, lw, sw, and beq that the processor already implemented, the designer figured that certain software does the following instructions extensively cs \$t \$s1 \$s2; cslw \$t \$s1 \$s2; cslwcs \$t \$s1 \$s2 . Besides the usual PC handling and instruction fetch as before, the cs instruction is described as: \$t <= max(\$s1, \$s2) The cslw does the following: \$t <=memory [ max(\$s1,\$s2)] The cslwcs instruction the following: \$t <= max{\$s1, memory[ max (\$s1, \$s2)]} So now you see that cs and lw in above names stand for compare_select and loadword. The designer plans to modify the datapath and control signal based on the processor showed in next page. It’s a textbook processor with some missing blocks and wiring to fill in. The components he can use are any of the blocks already present in the design and the generalized GALU (showed above) with an additional output GREATER that equals to 1 if Input1-Input2 >0, and equals to 0 if Input1-Input2 =< 0. input1 Input 2 zero Greater output GALU ALUcontrol box1 box2 A BC
Questions: a). Describe below in words and fill in box 1 the blocks needs to be added in order to implement the cs and cslw instruction. Furthermore add in and draw in box 2 any additional blocks to implement the cslwcs instruction. (hint: think about doing so by adding GALU(s), MUX(es),AND(s) etc., and possibly new control signal(s)) i) For cs and cslw: The datapath needs minor changes. Basically, needs a GALU1. The Greater1 signal is used to select between \$s1 and \$s2 (so a mux is needed), and another control signal NEWC1 is used to choose between this output and the GALU data output (another mux is needed). In total 1 GALU and 2 mux needed The datapath needs minor changes. Basically, ALU needs to be replaced by GALU1. The Greater1 signal is used to select between \$s1 and \$s2 (so a mux is needed), and another control signal NEWC1 is used to choose between this output and the GALU data output (another mux is needed). In total 1 GALU and 2 mux needed ii) For cslwcs: One way to add cslwcs is add another generalized ALU2 after the right most mux to compare the loaded word and \$s1 (subtraction and generate GREATER2), and then add a new mux with control signal NewC2 such that NewC2&Greater2 selects the value between \$s1 and memory output. In general 1GALU, 1 mux and 1 AND are needed. Box 1 Read data 1 Mux b output To AND gate To Memory and Mux c Box 2 Mux c output To Reg file write data

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b). Fill in the control table below with X, 0 or 1. Add in new column(s) if you need new control signal(s) ( you may not need all three columns) c). Please point out the critical path , estimate for him the critical path delay in ns , and hence determine the fastest clock rate in MHz . Finally use a program given below to evaluate the processor . Use the following delay parameters (ignore hold time and
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## This note was uploaded on 05/17/2009 for the course CS 152 taught by Professor Kubiatowicz during the Spring '04 term at Berkeley.

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Computer Science 152 - Fall 2000 - Brodersen - Midterm 1 -...

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